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`timescale 1 ns/1 ps
module control_unit_statemac( add1_temp,
add2_temp,
op_code_temp,
sel_temp,
d_bus,
push_temp,
pop_temp,
go_temp,
clkin_temp,
pclk,rs,
clk,
rst,
int0,
int1,
ir,
dz,
z,
cy);
output [13:0] add1_temp, add2_temp;
output [2:0] op_code_temp;
output [3:0] sel_temp;
inout [15:0] d_bus;
output pclk, go_temp, push_temp, pop_temp, clkin_temp, rs;
input clk, rst, int0, int1, dz, z, cy;
input [21:0] ir;
reg [13:0] add1_temp, add2_temp;
reg [2:0] op_code_temp;
reg [3:0] sel_temp;
reg [15:0] d_out, d_bus_temp;
reg pclk, push_temp, pop_temp, go_temp, clkin_temp, rs;
parameter reset=18'd0,
a=18'd1,
b=18'd2,
c=18'd4,
d=18'd8,
e=18'd16,
f=18'd32,
g=18'd64,
h=18'd128,
i=18'd256,
j=18'd512,
k=18'd1024,
l=18'd2048,
m=18'd4096,
n=18'd8192,
o=16384,
p=18'd32768,
q=18'd65536,
r=18'd131072;
parameter a_add = 7'b0110010,
b_add = 7'b0110011,
c_add = 7'b0110100,
pc_add = 7'b0010000,
stack_add = 7'b0101111;
reg [17:0] p_state, n_state;
always @(posedge clk) begin
if (rst)
p_state <= reset;
else
p_state <= n_state;
end
always @* begin //(p_state)
case(p_state)
reset : begin
n_state <= a;
op_code_temp <= 3'bzzz;
add1_temp[13:0] <= 14'hzzzz;
add2_temp[13:0] <= 14'hzzzz;
go_temp <= 1'b0;
pclk <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0;
rs <= 1'b1;
end
a : begin
casex(ir)
22'b000001xxxxxxxxxxxxxxxx : begin
n_state <= l;
@(posedge clk) begin
add1_temp[6:0] <= ir[14:8];
add1_temp[13:7] <= stack_add;
sel_temp[3:0] <= 4'b0011;
push_temp <= 1'b1;
//add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
//d_out[15:0] <= 16'hzzzz;
//op_code_temp[2:0] <= 3'bzzz;
/*pop_temp <= 1'b0;
go_temp <= 1'b0;
clkin_temp <= 1'b0;*/end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b000010xxxxxxxxxxxxxxxx : begin
n_state <= m;
@(posedge clk) begin
add1_temp[6:0] <= stack_add;
add1_temp[13:7] <= ir[14:8];
pop_temp <= 1'b1;
sel_temp[3:0] <= 4'b0011;
/*add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
push_temp <= 1'b0;
op_code_temp[2:0] <= 3'bzzz;
go_temp <= 1'b0;
d_out[15:0] <= 16'hzzzz;
clkin_temp <= 1'b0; */
end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b001xxxxxxxxxxxxxxxxxxx : begin
n_state <= b;
@(posedge clk) begin
add1_temp[13:7] <= a_add;
add1_temp[6:0] <= ir[6:0];
add2_temp[13:7] <= b_add;
add2_temp[6:0] <= ir[14:8];
sel_temp[3:0] <= 4'b1111;
/*d_out[15:0] <= 16'hzzzz;
op_code_temp[2:0] <= 3'bzzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0; */
end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b010xxxxxxxxxxxxxxxxxxx : begin
n_state <= d;
@(posedge clk) begin
d_out[7:0] <= ir[7:0];
add1_temp[13:7] <= a_add;
//add1_temp[6:0] <= 7'bzzzzzzz;
add2_temp[13:7] <= b_add;
add2_temp[6:0] <= ir[14:8];
sel_temp[3:0] <= 4'b1110;
/*d_out[15:8] <= 8'hzz;
op_code_temp[2:0] <= 3'bzzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0;*/
end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b011xxxxxxxxxxxxxxxxxxx : begin
n_state <= e;
@(posedge clk) begin
add1_temp[13:7] <= ir[14:8];
add1_temp[6:0] <= ir[6:0];
sel_temp[3:0] <= 4'b0011;
/*add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
d_out[15:0] <= 16'hzzzz;
op_code_temp <= 3'bzzz;
go_temp <= 1'b0;
pclk <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0;*/
end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b100xxxxxxxxxxxxxxxxxxx : begin
n_state <= g;
@(posedge clk) begin
d_out[7:0] <= ir[7:0];
add1_temp[13:7] <= ir[14:8];
sel_temp[3:0] <= 4'b0010;
/*add1_temp[6:0] <= 7'bzzzzzzz;
add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
op_code_temp[2:0] <= 3'bzzz;
d_out[15:8] <= 8'hzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0;*/ end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b101001xxxxxxxxxxxxxxxx : begin
n_state <= h;
@(posedge clk) begin
add1_temp[13:7] <= stack_add;
add1_temp[6:0] <= pc_add;
sel_temp[3:0] <= 4'b0011;
/*add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
op_code_temp[2:0] <= 3'bzzz;
d_out[15:0] <= 16'hzzzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0;*/ end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b101010xxxxxxxxxxxxxxxx : begin
n_state <= j;
@(posedge clk) begin
add1_temp[13:7] <= pc_add;
add1_temp[6:0] <= stack_add;
pop_temp <= 1'b1;
sel_temp[3:0] <= 4'b0011;
/*add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
d_out[15:0] <= 16'hzzzz;
op_code_temp[2:0] <= 3'bzzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
clkin_temp <= 1'b0; */ end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b110xxxxxxxxxxxxxxxxxxx : begin
n_state <= n;
@(posedge clk) begin
add1_temp[13:7] <= pc_add;
d_out[7:0] <= ir[15:8];
sel_temp[3:0] <= 4'b0010;
/*add1_temp[6:0] <= 7'bzzzzzzz;
add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
op_code_temp[2:0] <= 3'bzzz;
d_out[15:8] <= 8'hzz;
go_temp <= 1'b0;
push_temp <= 1'b0;
pop_temp <= 1'b0;
clkin_temp <= 1'b0; */
end
pclk <= 1'b0;
rs <= 1'b0;
end
22'b111001xxxxxxxxxxxxxxxx : begin
pclk <= 1'b0;
rs <= 1'b0;
if(dz==0) begin
n_state <= o;clkin_temp <= 1'b1;
end
else
n_state <= q;
end
22'b111010xxxxxxxxxxxxxxxx : begin
pclk <= 1'b0;
rs <= 1'b0;
if(z!=0)
n_state <= o;
else
n_state <= q;
end
22'b111011xxxxxxxxxxxxxxxx : begin
if(z==0) n_state <= o;
else n_state <= q;
pclk <= 1'b0;
rs <= 1'b0;
end
22'b111100xxxxxxxxxxxxxxxx : begin
pclk <= 1'b0;
rs <= 1'b0;
if(cy==0)
n_state <= o;
else
n_state <= q;
end
22'b111101xxxxxxxxxxxxxxxx : begin
pclk <= 1'b0;
rs <= 1'b0;
if(cy!=0)
n_state <= o;
else
n_state <= q;
end
default : n_state <= reset;
endcase
end
b : begin
n_state <= c;
@(posedge clk) begin
//add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
//add1_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
sel_temp[3:0] <= 4'b0000;
op_code_temp <= ir[18:16];
go_temp <= 1'b1;
end
end
c : begin
n_state <= a;
@(posedge clk) begin
add1_temp[13:7] <= ir[14:8];
add1_temp[6:0] <= c_add;
sel_temp[3:0] <= 4'b0011;
op_code_temp <= 3'bzzz;
go_temp <= 1'b0;
end
pclk <= 1'b1;
end
d : begin
n_state <= c;
@(posedge clk) begin
//add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
//add1_temp[13:7] <= 7'bzzzzzzz;
sel_temp[3:0] <= 4'b0000;
op_code_temp <= ir[18:16];
go_temp <= 1'b1;
end
end
e : begin
n_state <= f;
@(posedge clk)
sel_temp[3:0] <= 4'b0000;
//add1_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
end
f : begin
n_state <= a;
pclk <= 1'b1;
end
g : begin
n_state <= f;
@(posedge clk) begin
d_out[7:0] <= 8'hzz;
sel_temp[3:0] <= 4'b0000;
//add1_temp[13:7] <= 7'bzzzzzzz;
end
end
h : begin
n_state <= i;
@(posedge clk)
push_temp <= 1'b1;
end
i : begin
n_state <= a;
@(posedge clk) begin
add1_temp[13:7] <= pc_add;
d_out[7:0] <= ir[15:8];
sel_temp[3:0] <= 4'b0010;
//add1_temp[6:0] <= 7'bzzzzzzz;
end
end
j : begin
n_state <= k;
@(posedge clk)begin
pop_temp <= 1'b0;
sel_temp[3:0] <= 4'b0000;
end
end
k : begin
n_state <= a;
end
l : begin
n_state <= f;
@(posedge clk) begin
push_temp <= 1'b0;
sel_temp[3:0] <= 4'b0000;
end
end
m : begin
n_state <= f;
@(posedge clk) begin
pop_temp <= 1'b0;
sel_temp[3:0] <= 4'b0000;
end
end
n : begin
n_state <= k;
@(posedge clk) begin
sel_temp[3:0] <= 4'b0000;
//add1_temp[13:7] <= 7'bzzzzzzz;
d_out[7:0] <= 8'hzz;
end
end
o : begin
n_state <= p;
@(posedge clk) begin
sel_temp[3:0] <= 4'b0010;
add1_temp[13:7] <= pc_add;
d_out[7:0] <= ir[15:8];
end
end
p : begin
n_state <= a;
@(posedge clk) begin
sel_temp[3:0] <= 4'b0000;
//add1_temp[13:7] <= 7'bzzzzzzz;
d_out[7:0] <= 8'hzz;
end
end
q : begin
n_state <= r;
/*@(posedge clk) begin
add1_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
d_out[15:0] <= 16'hzz;
push_temp <= 1'b0;
pop_temp <= 1'b0;
go_temp <= 1'b0;
clkin_temp <= 1'b0;
op_code_temp[2:0] <= 3'bzzz; end */
end
r : begin
n_state <= a;
/*@(posedge clk) begin
add1_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
add2_temp[13:0] <= 14'bzzzzzzzzzzzzzz;
d_out[15:0] <= 16'hzz;
push_temp <= 1'b0;
pop_temp <= 1'b0;
go_temp <= 1'b0;
clkin_temp <= 1'b0;
op_code_temp[2:0] <= 3'bzzz; end */
pclk <= 1'b1;
end
default : n_state <= reset;
endcase
/*@(posedge clk)
begin
add1[13:0] <= add1_temp[13:0];
add2[13:0] <= add2_temp[13:0];
//data[15:0] <= d_bus_temp[15:0];
op_code[2:0] <= op_code_temp[2:0];
push <= push_temp;
pop <= pop_temp;
clkin <= clkin_temp;
go <= go_temp;
d_bus_temp <= d_out[15:0];
end
*/
end // always @ *
always @(posedge clk)
d_bus_temp[15:0] <= d_out[15:0];
assign d_bus[15:0] = d_bus_temp[15:0];
endmodule