Priority based Place and Route in FPGA

[imbichie]

Hi All,

I am using Xilinx Kintex 6 Ultra-Scale FPGA for my design.
Synplify Premier for Synthesis and Vivado for PnR.
My fpga utilization is more than 93%.
I am facing some critical timing violations in one of my module.
Is it possible to do a priority based place and route, so I can give the first priority to this module and place and route his module first for avoiding critical timing violations.

For example, say I have 3 modules mod_A, mod_B and mod_C.
If I am facing critical timing violations in mod_A.
So I wants to do the Place and Route by giving the first priority as mod_A.
So once the mod_A is routed for achieving the best timing, then I will route the mod_B and mod_C later by preserving the mod_A PnR.

Please let me know is there any option for doing this kind of priority based PnR in Vivado ?

 

[dpaul]

Which Vivado version are you using? I would suggest you to use the latest version.

Cannot directly answer your query, I have never done it, but this is what I have to say...
From my previous experience with Xilinx ISE, I had observed that if device utilization is >80% then it was difficult to meet timing. If the design cannot be changed then the only option at that time was to use a bigger device. I am sure this has improved in Vivado. Now since there are various Vivado versions, so using the latest one might give different results.

 

[pbernardi]

Check UG903, there are some nice recommendations regarding constraints there, including priority routing if I am not mistaken. Remember you can ignore false paths and most time ignore resets timings.

Also, you can try to put some main blocks (DSP, Block RAMs, PLL) of mod_A in a fixed position.

 

[ads-ee]

Just took a look at UG903 and there isn't anything in there about priority routing, so you are mistaken. There isn't anything like priority placement and routing at all in Vivado AFAIK.

The closest thing is using the partitions and or partial reconfiguration. I would try partitioning the design. You can place and route partitions separately if you have a partial reconfiguration license otherwise it's the entire design, but if a partition meets timing you can write out a dcp for that partition and lock that partition (don't remember the exact terminology). Doing this will give you an incremental flow.

But given that you are at >93% you may not be able to partition your design, that is an extremely high utilization anything over 80% get problematic unless the design has a very simple architecture with little cross module signals, e.g. a bunch of shift registers that take up 93% of the resources.

 

[TrickyDicky]

Doesnt Vivado allow something like quartus logiclock regions? here you assign anything from single registers to whole entites to a region of the chip, and it pretty much gives priority to the chosen entites. It's used to stop the fitter spreading a design over the chip to try and get it to meet timing.

 

[ads-ee]

Doesnt Vivado allow something like quartus logiclock regions? here you assign anything from single registers to whole entites to a region of the chip, and it pretty much gives priority to the chosen entites. It's used to stop the fitter spreading a design over the chip to try and get it to meet timing.

Yeah it's called partitioning, which I describe above.

 

[imbichie]

Hi All,

Thank you for your time and replay.

@dpaul : Now I am using Vivado 2014.4, but I have the flexibility to choose any vivado version with license, if the other higher version of vivado solves my issue.

@pbernardi : I already checked the UG903 constraint guide before I starting the synthesis, but there is nothing about priority PnR. I already moved my adders, XOR logic to DSP blocks and also used BRAM blocks well.

Regarding partitioning the design, I have heard about this, and I thought of doing this but I dont have an experience on this. As ads-ee said, my utilization is more than 93%, so if the partition is not done well, it may cause more utilization or more timing violations.

I got another solution from the vivado implementation guide, I am going to try this : https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug904-vivado-implementation.pdf
UG904, page no 84. script 2 and 3.

Thank you for your suggestion and time.