I have a clock generator in my design, composed of some cascaded inverters. However, during synthesis the tool deleted/ignored most of the inverters making an incorrect hardware implementation. Any RC script command to preserve the clock generator module ? TIA
The reported behaviour can be found with any HDL compiler, cause it is required to minimize the logic. Ring oscillators are regarded as useless delays. The below synthesis attributes are working with Altera Quartus, but should also help with other compilers. If not, consult the manual for specific syntax. Alternatively to synthesis attributes in HDL, also tool specific constraints can be used.
Code:
// synthesis attribute to keep combinational signals in Verilog
wire my_wire /* synthesis keep = 1 */; // Verilog
(* keep = 1 *) wire my_wire; // Verilog-2001
-- synthesis attribute to keep combinational signals in VHDL
signal my_wire: bit;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;