ryodan_2004
Newbie level 3
synthesis keep
I have a clock generator in my design, composed of some cascaded inverters. However, during synthesis the tool deleted/ignored most of the inverters making an incorrect hardware implementation. Any RC script command to preserve the clock generator module ? TIA
I have a clock generator in my design, composed of some cascaded inverters. However, during synthesis the tool deleted/ignored most of the inverters making an incorrect hardware implementation. Any RC script command to preserve the clock generator module ? TIA