arash rezaee
Member level 5
Hi every one. I tried to write a vhdl code for pre-emphasis of 50us and I will attach the file. the problem is in lowest frequency ( less than 1KHz) it is fine but above 2KHz it will increase amplitude of signal more ( in 4KHz it must 4dB but it is 5.5dB) for highest frequency is not bad but in the middle frequencies it is not good. Can anyone help me and tell where is the problem. sampling rate is 95KHz with sinusoidal signal and 16 bit input/output.
regards
Arash
regards
Arash