[SOLVED] practical cmos design of sample and hold circuit-- need help urgent

[Basu_Gouda]

Hi

I am designing the ADC circuit for 125MSPS for this I need to design a sample and hold circuit. I am using the 0.35u technology by tsmc. I succeeded in designing the opamp with 1Mhz frequency but unable to go further kindly help me out with this its bit of urgent.

Thanks in advance

 

[dick_freebird]

You need way, way better than 1MHz BW for that fast
of a conversion rate.

I'd suggest that you think of track/hold rather than
sample/hold (the latter implying a shorter sample
window to me, short window makes the settling time
a greater problem). Depending on the loading of the
"S/H" you might have a bare cap and switch, or need
a follower buffer. A buffered backend can also let you
get away with less hold capacitor (perhaps as little
as the buffer's natural front end capacitance) which
eases the sampling settling time problem for the front
end (but makes you more sensitive to switch charge
injection). If you have a large input common mode
range them this (charge injection) will make for some
more elaborateness in the front end and back end
switch design, to make charge balance common mode
insensitive.

You might consider schemes that make the frequency
compensation modal / variable, to address the usual
compromise between stability and slew rate / settling
time.

There should be many scholarly papers on ADC input
buffer amps and front end architectures. Most of them
held hostage behind various pay-walls, but often a
search for the authors and keywords will turn up
private copies shared freely elsewhere.

 

[Basu_Gouda]

Thanks for the reply at this moment I am focusing on building the high frequency opamp architecture I am unable find out the solution how to decide my mos sizes for the bandwidth

 

[dick_freebird]

Bandwidth comes from low impedance, low capacitance
and high current density. Pretty much the opposite of
low power CMOS op amp design styles.

I would recommend a couple of low-ish gain differential
stages and, since this is a sampled and probably "steppy"
application, some anti-windup clamping to keep the stages'
swing limited (against the return slew) in the interest of
settling time. Low-stage-gain lineups happen to be kind
of friendly to autozero schemes, which I expect you also
care about.