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pp for full chip or block

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vissu.com

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Hi All,

Can anybody inform me, what r the requirements for full chip power planning?
2. Can a block (or) tile owner can do his own power planning for his block without cosidering the top level?
3. Can anybody provide me the documents to do power planning for full chip which includes core ring width calculation, horizontal & vertical stripe width calculation, spacing b/w horizontal & verical stripes. Based on what requirements one does the above calculations?
4. While power planning do we need to consider IR drop.
5. Does a virtual clock exists in a block?

Iam very much thankfull if anybody provide me the documentation regarding the above questions.

Thanks,
vissu.
 

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