Power line width for oscillator layout

[danda821]

I am doing a layout of a oscillator. There will be about 10mA current through a power line (M1 and M2). I do not know how wide the metal should be to handle the current, how many vias to handle the current?
Is there any power line width equation as the one in PCB?
Thanks.

 

[noiseless]

power line width

chech the design manul to see if there is data

 

[Element_115]

Re: power line width

I don't know how big your board is etc... But 10mA is very small.
And if your frequency is high enough you should make sure your line/trace
width is matched to your system. For current handling you can find
some information on wire gages to get a rough idea of how much
metal you need. If this is a RF VCO you can look at Rogers web site
for power handling capabilities of their boards.

But at 10mA your not creating a lot of power anywhere.
(I)^2 x R = Watts

 

[tarkyss]

power line width

you can check your techfile, how much is the current density that is safe for m1 m2 and via

 

[rogerliu]

Re: power line width

The current density is 0.5mA/um~1mA/um on metal line normally, for detail data
please see chip design rule of foundry.

 

[Prasanna Kumar]

Re: power line width

Hi,

As a rule of thumb you can use 1um thickness for 1mA of current. so in ur case may use the metal line will be about 1oum or even more. Not only that the process u r using will tell u the width of the metal of have to use .

to know the maximum current your metal can carry u can use this formula

Imax = Jmax * W * t

Jmax is the maximum allowed ci\urrent density which will be specified in the rules
W is the width in microns
t is the thick ness of the metal

hope this helps you.

 

[ocarnu]

Re: power line width

Beside the 1ma/um rule or someting like 0.5ma/via (you should have the data in your fooundry/pdk data) make sure you check the voltage drop on the line. 10mA is enough to have several tens of mV difference. If this goes to current mirrors which should be matched is a disaster. +- 50mV in VGS or VBE is a lot. This is why you use a star connection in the layout.

 

[adam79416]

power line width

What is the process u choosed? about 1-2um/mA.

Added after 5 minutes:

Only a OSC consumes 10mA? CMOS or BIpolar? too huge. maybe u should modify ur circuits.