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Power Estimation after P&R

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kgeorge123

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vsdg cadence

Hi,

Does any one know if we can estimate the power(say in terms of current consumption) of the chip at the stage of PnR. Or at the latest stage which ever is possible. I wish to calculate Reset current (which would mean the leakage current of the chip) and say the current when it is running at 100MHz.
 

linuxluo

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hi,
yes, you can use voltagestorm from cadence to calculate the current.

linuxluo
 

joe2moon

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It's task of 2 stages ...
----------------------------------------------------------------------------
- 1) (static/dynamic) Power analysis
Tool used:
-- PowerMeter(Cadence), PowerTheater(Sequence), or PrimePower(Synopsys).

- 2) (static/dynamic) IR-drop analysis
Tool used:
-- RedHawk(Apache), VoltageStorm/VSDG(Cadence), CoolTime(Sequence), or Astro-Rail/PrimeRail(Synopsys).
 

kgeorge123

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Thank you for the tools info.At what stage can this power can be calculated.Is this like just at the GDSII stage or before it. I wish to know if it would model the current capabilites of the pads and output drivers etc.

Added after 1 hours 50 minutes:

Are these tools able to model High impedance states of some of outputs inside the chip. WHich means that there are some floating inputs inside the chips.
Would these tools take into account the floating nets and calculate currents?
 

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