Power delay product discrepany

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ksnf3000

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Hi All,

I have a query w.r.t power-delay-product of a digital circuit. I am calculating the total power(in eldo) and then computing the delay between the output and input. However I see a difference in the delay values when I measure for the clk rise and fall. At clk rise its around 21.5 ps and for clk fall its 45.74 ps

Why this discrepancy? Also, the circuit is a simple DDSLL xor 2i input where clk is precharged when its 0 and evaluation takes place when its 1.

Thanks,
/ksnf3000
 

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