One thing you must understand is that timing takes priority over area and power. The synthesis tool will honour timing first, and if possible will work to reduce area and power. That being said, just because you wrote an SDC property for power, it doesn't mean that the tool will consider it.
If you care about power, the best way to approach it is by executing a low-power flow. Turn on all power optimizations that are available to you at synthesis level, placecement level, CTS, routing, and so on. eg. clock gating.