power constraint in SDC constrant file

[preethi19]

Hello i am new to digital design and i am trying to learn how to design and implementation of digital circuits. I read SDC files are constant files where "the rules that are written to meet designs goal in terms of Area, Timing and Power to obtain the best possible implementation of a circuit".

So it seems like say if my aim is to design a circuit with say a power consumption of x. So i would not want a design that exceeds more than this. So do we mention this x requirement in the SDC file??? And we won't know the power consumption of a design till we estimate it. So what if i mention in the power constraint in the SDC file to be very low than x. Then what will happen? Will the design work or will any error be displayed. I am still in theory level so haven't started with the tool yet to know if any error or anything warning would occur. So kindly have tolerance with my question. Thank you!!!

 

[ThisIsNotSam]

One thing you must understand is that timing takes priority over area and power. The synthesis tool will honour timing first, and if possible will work to reduce area and power. That being said, just because you wrote an SDC property for power, it doesn't mean that the tool will consider it.

If you care about power, the best way to approach it is by executing a low-power flow. Turn on all power optimizations that are available to you at synthesis level, placecement level, CTS, routing, and so on. eg. clock gating.