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Power analysis in SoC Encounter

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Jul 7, 2009
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power analysis in soc encounter

Hi all,

I'm doing power analysis for u-processor with Encounter.
There are some modules such as an instruction memory customly designed.
Encounter sees this as a single cell, so I can not see the power map and IR drop inside this module.

Do you have any suggestions so that I can see these analysis results inside these modules as well?

Thank you in advance.

You should have Power detailed view for every one custom designed view ,already, before you decide to perform Power Analysis using Encounter based design flow.
Notated Detailed View (.cl view) can be denerated by yourself in case if you have GDS data.
Please look into 'libgen' utility user giude for get more details.

I pasted example of libgen command file below:

input_type pr_gds
lef_file_list {../../../SOC_DATA/diglib/lef/cmos18_5_1_typ_technology.lef}
gds_file_list {../../physical/gds/del_line_CDS.gds}

#cell_list_file ./SCRIPTS/cell_list.txt
cell_list { * }
# decap_cell_list { decap_9_ddl decap_NWring_9_corn decap_NWring_9_l decap_NWring_9_r }
decap_cell_list { }
# filler_cell_list { decap_9_ddl decap_NWring_9_corn decap_NWring_9_l decap_NWring_9_r }
filler_cell_list { }

setvar library_name DDL_del_line
setvar defgds_mbb_layername prBoundary
setvar tech_file ../../../SOC_DATA/diglib/qrc/cmos18_5_1_typ.tch
setvar gds_extractor_command_file ./SCRIPTS/xtc.cmd

generic_ground_names 0.00 {vss VSS vsss}
generic_power_names 1.98 {vdd VDDLOGIC vdds}

include ./SCRIPTS/
include ./SCRIPTS/libgen_lef_def.map_5_1

setvar generate_port_powerview true
setvar generate_detailed_powerview true
detailed_powerview_cell_list {del_line}

spice_model_file ../../../pdk/models/spectre/ASE_onc18.spectre

setvar default_frequency 100e+6
setvar extract_r_only true


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Thank you for your information.

But I couldn't find the 'libgen' documentation by googling.
Can you please direct it?

The 'libgen' utility is a part of SOC Encounter Platform as Voltage Storm. So, I would advice to you to get started with <SOC installation root>/doc/dataprep/dataprep.pdf document (Chapter 5: LibGen: Creating Cell Libraries)
the document's tasks, which you should pay attention on:
If your source is some GDS data, you have to use transistor level netlist for DC simulation and you should be focused on libgen's "PR_GDS" flow.
If your source data is cell based (and you have .cl view for these cell) then you should review libgen's "PR_LEF" flow, this flow does not use transistor level netlist for simulation, but just replaces all cells by current sources (or by subcircuits which contain current sources and parasitic RC network) and perform a simulation using passive element (R and C) and current sources.
The "PR_GDS" flow takes more machine resources and simulation time in comparison with the "PR_LEF" flow.
Besides, libgen supports some "mixed" "PR_LEF_GDS" flow, so the utility is flexible enough.

It's been a while. Anyway, thank you for your help.
I'm following the pr_gds flow.
But, there're errors I can't figure out.

Here is my libgen.cmd file.

input_type pr_gds
lef_file_list { csm13_6lm_tech.lef InstrMem.lef }
# put each gds file in a separate line to bypass gds_file_list line limit
gds_file_list { InstrMem.gds2 }
cell_list { * }
setvar library_name library_IM_lef
setvar tech_file /export/home1/scratch/moongon/encounter/3DMAPSv05/techFiles/tch/chrt013g_1p6m_8k_typ.tch

setvar case_sensitivity_default true
setvar defgds_mbb_layername DEF_MBB

# generate port power view
setvar generate_port_powerview true
setvar generate_graybox_data false
setvar default_power_voltage 1.5
generic_power_names 1.500 { VDD }
generic_ground_names 0 { VSS }

# generate detailed power view
setvar generate_detailed_powerview true
setvar default_frequency 416.667e6
setvar gds_extractor_command_file xtc.cmd
thunder_model_table_directory thunder
netlist_file_list { InstrMem.cdl }
spice_model_file sm142001-1g.hspice
detailed_powerview_cell_list { * }

If I include both lef & gds mapping files,
it gives errors complaining layers (M1, M2, ... ,V4, V5) are redifined in the command file.

If I comment out lef mapping file,
then it gives an error as follows:
FATAL: Under the Libgen flow, XTC requires at least one LEF output metal layer from GDS to be marked as a port layer. This layer must contain text labels that identify the locations of the ports of the cell. Use the port option of the layer commands (metal, diff, poly, via, well, li, layer) to idetnify the layers that should be treated as LEF ports.

Lef mapping:
layer M1 lefdef METAL1
layer M2 lefdef METAL2
layer M3 lefdef METAL3
layer M4 lefdef METAL4
layer M5 lefdef METAL5
layer M6 lefdef METAL6
layer V1 lefdef VIA12
layer V2 lefdef VIA23
layer V3 lefdef VIA34
layer V4 lefdef VIA45
layer V5 lefdef VIA56

gds mapping:
diff DIFF gds 22
well DNWELL gds 12
well TNWELL gds 21
poly POLY gds 30 0
layer PIMP gds 31
layer NAT gds 5
layer DV gds 55
layer LVT gds 87
layer HVT gds 187
layer SB gds 49
layer RESISTOR gds 62
layer RES_MK gds 110 5
layer ESD gds 24
via CONT gds 33
metal M1 gds 34 0
metal M1 gds 34 5
metal M1 gds 34 10 port text_only
via V1 gds 35
metal M2 gds 36 0
metal M2 gds 36 5
metal M2 gds 36 10 port text_only
via V2 gds 38
metal M3 gds 42 0
metal M3 gds 42 5
metal M3 gds 42 10 port text_only
via V3 gds 40
metal M4 gds 46 0
metal M4 gds 46 5
metal M4 gds 46 10 port text_only
via V4 gds 41
metal M5 gds 81 0
metal M5 gds 81 5
metal M5 gds 81 10 port text_only
via V5 gds 82
metal M6 gds 126 0
metal M6 gds 126 5
metal M6 gds 126 10 port text_only
layer DEF_MBB gds 200
#layer OUTLINE gds 62 21

Can you give me some advice?
Also I'm wondering how to set DEF_MBB (bounding box) layer correctly in gds mapping file.
I used unused number, but this shouldn't be right.
And even though I don't want to use TableGen (in Thunder), if I comment it out, it gives an error.

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