Post-synthesis simulation problem due to RTL clock gating

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childs72

Member level 1
Hi guys,

I had implemented clock gating using RTL similar to below. It works well during RTL simulation. However, after synthesis, I perform simulation on post-syn netlist with sdf back-annotation. Simulation show the system does not function correctly.

Code:
assign cg__clk = clk || !clk_gate_en;
my_module my_inst ( .clk_in(cg__clk),
......);
Here is my hypothesis based on observaI understand that at post-synthesis stage, we have only ideal clock latency. However, due to the clock gate I inserted in RTL, I am seeing larger clock latency to registers inside "my_inst" (due to delay introduced by clock gate) compared to other non-clockgated registers outside of "my_inst"; this, in turns created hold time issue and the system is not able to function correctly.

Does my observation & hypothesis make sense? If yes, I believe I need to do something in order for the simulator (Cadence irun) to NOT annotate the delay at my clock gate cells. Can anyone suggest me how to do this?

Thanks!

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Also, when I tried to report_clock_gating -gated in DC, nothing related to above RTL is reported. Does DC not recognize the code as clock gating? What should I do?
Thanks.

jbeniston

I think report_clock_gating reports clock gating that power compiler inserts, not gating you have inserted by hand.

Your gating technique is possibly a bit unreliable, anyway. I'd suggest you look in your cell library for a clock gating latch, and instantiate that.

childs72

Member level 1
Thanks jbeniston. Agreed that I should look into the cell library for clock gating latch. Meanwhile, apart from using clock gating cell, is there anything improvement that can be done on my gating technique?

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