library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_df is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_df;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_df.all;
entity df is
port( CLK, D, RST : in std_logic; Q, Qbar : out std_logic);
end df;
architecture SYN_Behavioral of df is
component CKND16
port( I : in std_logic; ZN : out std_logic);
end component;
component BUFFD16
port( I : in std_logic; Z : out std_logic);
end component;
component INVD3
port( I : in std_logic; ZN : out std_logic);
end component;
component CKBD0
port( I : in std_logic; Z : out std_logic);
end component;
component MUX2ND0
port( I0, I1, S : in std_logic; ZN : out std_logic);
end component;
component INVD1
port( I : in std_logic; ZN : out std_logic);
end component;
component DFQD4
port( D, CP : in std_logic; Q : out std_logic);
end component;
component DFCND1
port( D, CP, CDN : in std_logic; Q, QN : out std_logic);
end component;
signal n11, n2, n3, n4, n5, n6, Qbar_port, n8, n9 : std_logic;
begin
Qbar <= Qbar_port;
Q_reg : DFCND1 port map( D => D, CP => CLK, CDN => n2, Q => n5, QN => n6);
Qbar_reg : DFQD4 port map( D => n8, CP => CLK, Q => n11);
U5 : INVD1 port map( I => n4, ZN => n3);
U6 : INVD1 port map( I => RST, ZN => n2);
U7 : MUX2ND0 port map( I0 => D, I1 => n3, S => RST, ZN => n8);
U8 : CKBD0 port map( I => Qbar_port, Z => n4);
U9 : INVD3 port map( I => n5, ZN => n9);
U10 : BUFFD16 port map( I => n11, Z => Qbar_port);
U11 : CKND16 port map( I => n9, ZN => Q);
end SYN_Behavioral;