[SOLVED] Post-Synthesis Simulation in Synopsys

[preethi19]

Hi i am learning Digital design flow. I had a simple D-flip flop vhdl code and the behaviour was verified and the test bench was simulated in Vivado and all was working fine. I took this .v file to Synopsys and was able to obtain the gate-level netlist.
In test bench for simulation we mention for the clk to start at certain time, for inputs to rise at particular time and etc. This is the gate-level netlist i obtained. The design has 3 inputs CLK,D and RST and 2 outputs Q and Qbar. So should i write a seperate test bench for this code??? Also i read in the site that post-synthesis simulation can be carried on by modelsim. Can i use vivado to test this gate-level netlist.. Also apart from this can anyone pls tell me what and why do we need an SDC and SDF file. I will be learning encounter next so do i need these files to proceed with the design flow??? Pls help!!!Thank you!!!

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_df is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_df;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_df.all;

entity df is

   port( CLK, D, RST : in std_logic;  Q, Qbar : out std_logic);

end df;

architecture SYN_Behavioral of df is

   component CKND16
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component BUFFD16
      port( I : in std_logic;  Z : out std_logic);
   end component;
   
   component INVD3
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component CKBD0
      port( I : in std_logic;  Z : out std_logic);
   end component;
   
   component MUX2ND0
      port( I0, I1, S : in std_logic;  ZN : out std_logic);
   end component;
   
   component INVD1
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFQD4
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   component DFCND1
      port( D, CP, CDN : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal n11, n2, n3, n4, n5, n6, Qbar_port, n8, n9 : std_logic;

begin
   Qbar <= Qbar_port;
   
   Q_reg : DFCND1 port map( D => D, CP => CLK, CDN => n2, Q => n5, QN => n6);
   Qbar_reg : DFQD4 port map( D => n8, CP => CLK, Q => n11);
   U5 : INVD1 port map( I => n4, ZN => n3);
   U6 : INVD1 port map( I => RST, ZN => n2);
   U7 : MUX2ND0 port map( I0 => D, I1 => n3, S => RST, ZN => n8);
   U8 : CKBD0 port map( I => Qbar_port, Z => n4);
   U9 : INVD3 port map( I => n5, ZN => n9);
   U10 : BUFFD16 port map( I => n11, Z => Qbar_port);
   U11 : CKND16 port map( I => n9, ZN => Q);

end SYN_Behavioral;

 

[dpaul]

So should i write a seperate test bench for this code???

No the same TB should suffice. Coz your design top-level ports remain the same which you must drive in the TB.

Can i use vivado to test this gate-level netlist.

Yes

Also apart from this can anyone pls tell me what and why do we need an SDC and SDF file.

This has been answered here previously....did you care to search?
https://www.edaboard.com/threads/201304/

 

[ThisIsNotSam]

Hi i am learning Digital design flow. I had a simple D-flip flop vhdl code and the behaviour was verified and the test bench was simulated in Vivado and all was working fine. I took this .v file to Synopsys and was able to obtain the gate-level netlist.
In test bench for simulation we mention for the clk to start at certain time, for inputs to rise at particular time and etc. This is the gate-level netlist i obtained. The design has 3 inputs CLK,D and RST and 2 outputs Q and Qbar. So should i write a seperate test bench for this code??? Also i read in the site that post-synthesis simulation can be carried on by modelsim. Can i use vivado to test this gate-level netlist.. Also apart from this can anyone pls tell me what and why do we need an SDC and SDF file. I will be learning encounter next so do i need these files to proceed with the design flow??? Pls help!!!Thank you!!!

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_df is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_df;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_df.all;

entity df is

   port( CLK, D, RST : in std_logic;  Q, Qbar : out std_logic);

end df;

architecture SYN_Behavioral of df is

   component CKND16
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component BUFFD16
      port( I : in std_logic;  Z : out std_logic);
   end component;
   
   component INVD3
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component CKBD0
      port( I : in std_logic;  Z : out std_logic);
   end component;
   
   component MUX2ND0
      port( I0, I1, S : in std_logic;  ZN : out std_logic);
   end component;
   
   component INVD1
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFQD4
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   component DFCND1
      port( D, CP, CDN : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal n11, n2, n3, n4, n5, n6, Qbar_port, n8, n9 : std_logic;

begin
   Qbar <= Qbar_port;
   
   Q_reg : DFCND1 port map( D => D, CP => CLK, CDN => n2, Q => n5, QN => n6);
   Qbar_reg : DFQD4 port map( D => n8, CP => CLK, Q => n11);
   U5 : INVD1 port map( I => n4, ZN => n3);
   U6 : INVD1 port map( I => RST, ZN => n2);
   U7 : MUX2ND0 port map( I0 => D, I1 => n3, S => RST, ZN => n8);
   U8 : CKBD0 port map( I => Qbar_port, Z => n4);
   U9 : INVD3 port map( I => n5, ZN => n9);
   U10 : BUFFD16 port map( I => n11, Z => Qbar_port);
   U11 : CKND16 port map( I => n9, ZN => Q);

end SYN_Behavioral;

what is this code you have attached supposed to be? why did the synthesis of a flipflop generated 8 gates?
are you doing FPGA-like synthesis and hoping to import that in encounter and follow an ASIC-like flow? if that is the case, it is so so wrong

 

[preethi19]

yes i am learning ASIC design flow. I am following a tutorial video that i found online i took a vhdl code for a simple d flip flop simulated and verified it in modelsim. Then in synopsys design vision i sythesized the d flip flop and mapped it to the technology file and generated the gate-level netlist (which is the code that i have attached) and now i am trying to verify the logic of the gate level netlist in modelsim with the same previous testbench. And wen i did this the input logics are as i describe in the test bench but outputs are turning out as undefined. Could you kindly let me know wer i am going wrong so i can correct it pls.. Thanks for the reply!!!

 

[ThisIsNotSam]

yes i am learning ASIC design flow. I am following a tutorial video that i found online i took a vhdl code for a simple d flip flop simulated and verified it in modelsim. Then in synopsys design vision i sythesized the d flip flop and mapped it to the technology file and generated the gate-level netlist (which is the code that i have attached) and now i am trying to verify the logic of the gate level netlist in modelsim with the same previous testbench. And wen i did this the input logics are as i describe in the test bench but outputs are turning out as undefined. Could you kindly let me know wer i am going wrong so i can correct it pls.. Thanks for the reply!!!

I am still not sure why a single flop would become 8 gates. something is wrong.

as to your simulation, check the basics. reset should be working, and the clock should be advancing. take a screenshot of your waveform and post here if you still can't find the issue.

 

[preethi19]

Thank you for the reply!!! That synthesized netlist code of the flip flop that i previously added is with input and output delay. The synthesized netlist is much simpler if i didn't mention any timing constraints. Also i am able to simulate for the gate-level netlist in modelsim (i created another netlist file without any constraints and tested it with the previous testbench and i am able to see the logic of the output Q is working correctly. But that of Qbar logic is coming out to be incorrect. I have attached the codes of RTL and gate-level netlist vhdl codes.. Have also attached an image of the post-synthesis waveform..Kindly have a look...



RTL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity df is
    Port ( CLK : in STD_LOGIC;
           D : in STD_LOGIC;
           Q : out STD_LOGIC;
           Qbar : out STD_LOGIC);
end df;

architecture Behavioral of df is

begin
    process(CLK)
    
    begin
    
     if(CLK='1' and CLK'EVENT) then
    Q<=D;
    Qbar <= not(D);
      end if; 
      end process;

end Behavioral;

Netlist

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_df is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_df;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_df.all;

entity df is

   port( CLK, D : in std_logic;  Q, Qbar : out std_logic);

end df;

architecture SYN_Behavioral of df is

   component CKND0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFQD1
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal n1 : std_logic;

begin
   
   Q_reg : DFQD1 port map( D => D, CP => CLK, Q => Q);
   Qbar_reg : DFQD1 port map( D => n1, CP => CLK, Q => Qbar);
   U4 : CKND0 port map( I => D, ZN => n1);

end SYN_Behavioral;

 

[dpaul]

I missed the part that synth was done with Synopsys.
No then the netlist simu. can't be done in Vivado.

I would like to point out that in #6, you are writing code for ASIC, so where is your reset signal?
All FFs must be 1st reset.

 

[ThisIsNotSam]

Thank you for the reply!!! That synthesized netlist code of the flip flop that i previously added is with input and output delay. The synthesized netlist is much simpler if i didn't mention any timing constraints. Also i am able to simulate for the gate-level netlist in modelsim (i created another netlist file without any constraints and tested it with the previous testbench and i am able to see the logic of the output Q is working correctly. But that of Qbar logic is coming out to be incorrect. I have attached the codes of RTL and gate-level netlist vhdl codes.. Have also attached an image of the post-synthesis waveform..Kindly have a look...

View attachment 129496

RTL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity df is
    Port ( CLK : in STD_LOGIC;
           D : in STD_LOGIC;
           Q : out STD_LOGIC;
           Qbar : out STD_LOGIC);
end df;

architecture Behavioral of df is

begin
    process(CLK)
    
    begin
    
     if(CLK='1' and CLK'EVENT) then
    Q<=D;
    Qbar <= not(D);
      end if; 
      end process;

end Behavioral;

Netlist

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_df is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_df;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_df.all;

entity df is

   port( CLK, D : in std_logic;  Q, Qbar : out std_logic);

end df;

architecture SYN_Behavioral of df is

   component CKND0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFQD1
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal n1 : std_logic;

begin
   
   Q_reg : DFQD1 port map( D => D, CP => CLK, Q => Q);
   Qbar_reg : DFQD1 port map( D => n1, CP => CLK, Q => Qbar);
   U4 : CKND0 port map( I => D, ZN => n1);

end SYN_Behavioral;

check your netlist, you will see that you have two flops, not a single one. that is because you wrote your RTL like that.
that is why Q and Qbar are not what you would expect.

 

[ads-ee]

I missed the part that synth was done with Synopsys.
No then the netlist simu. can't be done in Vivado.

I would like to point out that in #6, you are writing code for ASIC, so where is your reset signal?
All FFs must be 1st reset.

They started this thread originally in the Programmable logic section, I noticed this thread too late to give an infraction and merge it with the previous thread.

The original design was using the FPGA feature that powers on registers with GSR being active initially. I asked about that in their other thread and mentioned they could shift the control signals to after the GSR, but they abandoned that thread and started this one.

You can also simulate a netlist from synopsys as long as you have all the RTL library models for the netlist code, just compile those into the work library along with your code Vivado and it will simulate fine. I did that when I was running a simulation with both an ASIC and my FPGA in the same testbench (of course this was slow, but it did work).