chikaofili
Junior Member level 3
Please can anyone take a look at this code and see if I am using the wrong programming method ( I just learnt how to program in verilog recently)
When I use the .vo as a replacement in my topmodule, I get nothing as an output.. But I see that my input and enable signal is write. But all the other waveforms look weird to me
fmean .vo is too large
When I use the .vo as a replacement in my topmodule, I get nothing as an output.. But I see that my input and enable signal is write. But all the other waveforms look weird to me
Code:
module fmean (
CLK, //Clock
reset, //Reset
en,
Xin, //Xin
Xin_mean, //mean of CFA
f_mean // Indicate if the this test has been done
);
parameter INT_WIDTH = 20 ;
parameter FRAC_WIDTH = 12 ;
parameter FIXED_WIDTH = INT_WIDTH+FRAC_WIDTH;
parameter ADD_WIDTH = 18 ;
parameter MEM_SIZE = 8;
parameter MxN= 64;
input CLK;
input reset;
input en;
input [FIXED_WIDTH-1:0] Xin;
output reg f_mean;
output reg [FIXED_WIDTH-1:0] Xin_mean; // maybe add a reg so the mean does not get updated
//SUM REG: always increase based on log2(MxN) to prevent overflow eg. log2(65536)=16 + normal bits
// OFLOW_WIDTH= log (64)=6;
//parameter OFLOW_WIDTH=6;
parameter OFLOW_WIDTH=16;
parameter TEMP_WIDTH= OFLOW_WIDTH +FIXED_WIDTH;
//reg [TEMP_WIDTH-1:0] Xsum; // maybe add a reg so the mean does not get updated
//parameter TEMP_WIDTH= OFLOW_WIDTH +FIXED_WIDTH;
reg [TEMP_WIDTH-1:0] Xsum /* synthesis ramstyle = "no_rw_check" */;
reg en_mean;
// Address (Just a counter)
reg [ADD_WIDTH-1:0] Addr;
always @(posedge CLK) begin
if(!reset)
begin
Addr <=0;
Xsum <=0;
Xin_mean <=0;
f_mean <=0;
en_mean <=0;
end
else if ((en) &&(en_mean==0)&&(f_mean==0))
begin
if(Addr>=MxN-1)
begin
Xsum<=Xsum + Xin;//{Xin,12'd0};
Xin_mean<=Xsum[31:0];
en_mean<=1;
f_mean<=0;
end
else
begin
Xsum<=Xsum + Xin;//{Xin,12'd0};
Addr <= Addr +1;
Xin_mean<=Xsum[31:0];
end
end
else if ((en) && (en_mean==1)&&(f_mean==0))
begin
//Xin_mean<=Xsum/MxN + Xin/MxN; //{Xin,12'd0}/MxN; no shifting because MxN is integer
Xin_mean<=(Xsum + Xin)>>16;
Addr<=0;
//en_mean<=0;
f_mean<=1;
end
else if (!en)
begin
f_mean <=0;
en_mean <=0;
Xsum <=0;
Xin_mean<=0;
end
end //end of always
endmodule
fmean .vo is too large