You must have some metal lines floating on the layout. This is ignored in LVS.
Either you find and eliminate it, or go to the netlist and place a large resistor (for example 1e12 ohm) from every floating node to gnd.
I don't think this is a serious problem. With DCSTEP and GMINDC option the simulator can give correct results, and similar problem also happened during schematic pre-simulation.