Hello,
Debug is dependent on so many parameters like jbeniston hastold "All chips are failing?".
We have to analyze below things :
1. Which pattern failing (chain test, stuck-at or transition?)
2. All chips are failing for all the voltage variance?. Look at the shmoo plot (you will get information about shmoo plot on google).
3. I have also not the hands on experience but some analysis are done at the tester level also. There after we are applying those failing patterns with failing logs to ATPG. We can have just idea about the fault by doing Diagnosis in the ATPG tool itself.