Post Silicon Debug Issues

[Shankhy]

Hi all,

I wanted to know issues regarding post silicon debug like what happens when ATPG patterns fails in tester? What will be the approach to debug them?

 

[jbeniston]

Read the failing patterns and outputs back in to the ATPG s/w and it can tell you where the fault is.

 

[Shankhy]

Thanks for the reply...but can you tell me normally under which conditions the patterns can fail in the tester? I have also studied somewhere that generating low power patterns can sometime help in fixing this kind of issue? Is that correct?..

 

[jbeniston]

Are all your chips failing, or just a few?

Do your ATPG patterns pass in gate-level, SDF annotated, simulation?

 

[Shankhy]

No i just asked this question for knowledge purpose..I am not actually working on post silicon debug..

 

[maulin sheth]

Hello,

Debug is dependent on so many parameters like jbeniston hastold "All chips are failing?".
We have to analyze below things :
1. Which pattern failing (chain test, stuck-at or transition?)
2. All chips are failing for all the voltage variance?. Look at the shmoo plot (you will get information about shmoo plot on google).
3. I have also not the hands on experience but some analysis are done at the tester level also. There after we are applying those failing patterns with failing logs to ATPG. We can have just idea about the fault by doing Diagnosis in the ATPG tool itself.

 

[Shankhy]

Thanks for the reply maulin...Just wanted to understand that I studied somewhere that due to power variance also chip sometimes fail on the tester so it can rectified sometimes in atpg by generating low power patterns also..I think it comes under power aware atpg...Is the funda correct?

 

[maulin sheth]

yes. that is also true. During Scan patterns, too much switching activity occurs, so power is high.
But now most of the companies are doing Low Power ATPG.
Also doing power analysis on the without power aware atpg patterns to get the idea about power consumption of scan patterns.