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Junior Member level 2
Now I would like to run a post-layout simulation with sdf file back-annotated. The problem is that how I add the cell simulation verilog files of synthesis library into my final gate level netlist or verilog-xl simulator. There are more than 300 cell files, it's a very hard work to use include command to include all of them into my netlist. So what kind of measures can be taken to implement it.