Now I would like to run a post-layout simulation with sdf file back-annotated. The problem is that how I add the cell simulation verilog files of synthesis library into my final gate level netlist or verilog-xl simulator. There are more than 300 cell files, it's a very hard work to use include command to include all of them into my netlist. So what kind of measures can be taken to implement it.
i am not sure if this is correct answer, but may be u can trp this .. during synthesis for net list generation i guess ur not using the option of flatten .. if u can use this in ur script of DC the final generated netlist a single verilog life ,, u can use model sim with sdf file back annotation for post layout simulation .
please let me know if i am wrong , r u looking for it in other way..