For a 0.5um technology, the parasitics of a "good" layout shouldn't decrease/increase the schematic simulation values not more than about 10%... I layout a simple inverter using 0.5um CN05 technology.
As you've successfully extracted your layout, there should an extracted view and an extracted netlist be available, both already containing the parasitics.After extraction, LVS reported a matched layout with schematic.
Now, I want to run post-layout simulation. My questions:
1) How can I run ADE simulator (I'm using Spectre) with the extracted layout?
2) How can I extract the parasitics? Can I see the parasitic capacitance value and how?
This might be another possibility.3) Can I link the symbol to the extracted layout not the schematic?
For a 0.5um technology, the parasitics of a "good" layout shouldn't decrease/increase the schematic simulation values not more than about 10%
(concerning input capacitance, propagation delay, slew rate, max. operating frequency).
As you've successfully extracted your layout, there should an extracted view and an extracted netlist be available, both already containing the parasitics.
In the ADE Setup --> Design ..., select the extracted view,
This might be another possibility.
You want to use Hierarchy Editor and make a config view
for the simulation testbench schematic. For running post
layout sims you will open the config view (allowing the
schematic to open as well) and kick off the simulation
from that particular (schematic) window. In the config
view, you change the active view of the chip from
"schematic" to "analog_extracted" (or whatever the
name of the "refined" extracted netlist, so-prepared,
view is).
The connectivity (LVS) extracted netlist wants the
parasitics "massaged" (filtered, combined, etc.). There
is a menu based process for doing this. Last I looked
it was something like "refine extracted netlist" or like
that.
Right, concerning small parasitics (low propagation delay or high operating frequency).how can I know my layout is good? maintaining minimum DRC spacing between layers for example?
Yes!... the parasitic caps appear in the extracted layout. It means now I don't need to do QRC, Am I right?
I think the simulator neither found the (analog-)extracted view, nor the extracted netlist.I followed these steps but the simulation did not start and I can not probe any voltage or current in my schematic, Is there any reason making this problem?
This has already been answered by dick_freebird above, I guess.would you please advise how can I make a symbol using my extracted layout? I am using a schematic/Layout view not netlist.
File>New, same cellname as your simulation testbench,
type="config". Base view = schematic. This opens a
table-looking view and another window of your testbench.
Edit the switch-view and stop-view lists to match your
way of working. Update the views. In the config table
each master should now show which view type it's using.
You can alter this "surgically" (e.g. change the view of
the design-under-test, that sits in the testbench, from
"schematic" to "analog_extracted", so you are running
from the extracted view w/ refined parasitics).
When you change the view switching, then force a
re-evaluation (as lower hierarchy may be traversed in
a very different way). You can save the preferred
hierarchy (config view) and not have to re-jigger the
netlisting every time you come back to it.
At some later time you will File>Open the config view,
with schematic as well (check box), to simulate with
arbitrary configuration (re specific hierarchy for each
element) as you have been doing from schematic,
fixed view-switching (from master switch/stop list).
From the spawned schematic bound to the Hierarchy
Editor session, kick off your simulation in the usual
way.
You can also, I'm told, change specific individual
instances' switch/stop rather than all instances of
same master. But I never exercised this mode, before
stepping away from Cadence.
C-only extract I think is the default, simplest, oldest
and bothers the netlist only by addition of a whole lot of
shunt C elements.
RC extract actually has to break the netlist to insert
series R and these tools are newer, "bloatier" and have
to be invoked specifically.
By newer I mean a decade old instead of 3....
If you have C extraction in your extracted view, it means you are already using one of the extraction tools, possibly unknowingly.
Extraction mode - C, RC, R, or device-only - is one of the typical input settings to extraction tool, either in extraction tool command file, or in extraction tool GUI that you bring up from Virtuoso.
What is the default mode, that depends on local design flow settings.
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