Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Post layout and routing Cadence innovus verification

Status
Not open for further replies.

Abhi.ranjan

Junior Member level 1
Joined
Nov 9, 2022
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
88
How do we verify the functionality of the gds file created by innovus ? Or which tool we use to verify it?
 

1. GDS vs gate-level netlist (LVS)
2. Gate-level vs RTL (LEC)
3. RTL functional simulation
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top