i am currently practicing writing codes in VHDL for a spartan 3E FPGA. there are 4 LEDs that can be interfaced as ports and i have initialized them as so:
Code:
entity test is
port (
clock : in STD_LOGIC;
push_A : in STD_LOGIC;
push_B : in STD_LOGIC;
push_C : in STD_LOGIC;
push_D : in STD_LOGIC;
led_1 : out STD_LOGIC:= '0';
led_2 : out STD_LOGIC:= '0';
led_3 : out STD_LOGIC:= '0';
led_4 : out STD_LOGIC:= '0');
end test;
i have assigned each led its own variable but is it possible to assign them to an array instead?
eg: led[1] = '1'; <-- turns on led no.1
led[2] = '1'; <-- turns on led no.2 etc etc..
currently the only way i can do it is if i assign them to STD_LOGIC_VECTOR:
leds : out STD_LOGIC VECTOR (1 to 4) := "0000";
but i find it problematic to have to manipulate bits by shifting, AND, OR etc. i know it is possible to declare variable arrays, but i haven't been able to figure it out for declaring arrays in ports and have not found any help anywhere :-?
you can manipulate any bit of the above vector using
out(4) or out(3) or out(2) or out(1)
you can also change a smaller range like out(1 to 2) or out(2 to 4) etc
Are you trying to manipulate the out port? that is not allowed. Try using an internal intermediate signal signal for manipulation.
Code:
leds : out std_logic_vector(1 to 4);
...
signal leds_temp : std_logic_vector(1 to 4);
leds <= leds_temp;
process(clock)
begin
if rising_edge(clock) then
leds_temp <= inputs & leds_temp(1 to 3); --shift register
end if;
end process;