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How to declare a non input use in vhdl?

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Newbie level 6
Nov 28, 2015
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Hi there, I have a gradually input-upwards multiplexer. I designed a general 3 bit input multiplexer with one select input and one output. My question is, that in the first level MUX_0 from the 3 bit-input I am using only one bit, so accordingly

MUX_0 = 1 bit input usage
MUX_1 = 2 bit input usage
MUX_2 = 3 bit input usage

How I declare in MUX_0 and MUX_1 the non input bit in the port map? I have been already tried with the keyword "open" but it doesn't work. A small example of my code which doesn't work see below.

port map ( a(0) => carry_out_sign(0),
           b(0) => carry_out_sign(1),
           a(1) => open,
           b(1) => open,
           a(2) => open,
           b(2) => open,
           sel_c0 => carry_in(2),
           carry_out => mux_in_sign(2)


I would expect a useful default in the entity definition, if so you can simply omit the port association. You can also assign value 'X';
Not sure how one select input bit can control a 3-bit mux?

I did that with the value '0', but it throws me an error in Xilinx=> Formal port association for 'a' is non contiguous

You must assign all bits from the same array in a port map before assigning another bus. So assign all of a before you assign b.

Showing your code other than just your port map might help. And, as FVM said, how can you control a 3-input mux with one select line?

Generally, if you're not using an input, just assign it a value. Again, without seeing your code it's impossible to see why assigning a '0' caused a problem. The error you're seeing I think occurs when you assign a value of different size than the target, for example, assigning a single-bit value to a multi-bit vector.

My code is huge, each operand has 4 bit input, its a carry select adder. I need to fix it because I have to use the for - generate statement. Yeah you have right. The input must be something, otherwise won't work.

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