kajay
Newbie level 1
Homework for designing risc processor. I have 16 bit PC like this
Mux for PC source is
I have LPM generated 16 by 256 single port ROM for instruction memory
PC register port map is
Now the question is how can i port map the mem component because pc is 16 bit and address is 8 bit
Code:
signal pc_din, PC, pc_rel, pc_dir, pc_inc : std_logic_vector(15 downto 0); -- pc datapath
pc_inc <= pc + 1;
pc_dir <= pc(15 downto 13) & ADD;
pc_rel <= pc_inc + ext(15 downto 0);
Mux for PC source is
Code:
with PCSrc select
pc_din <= A when from_A,
pc_rel when from_pcrel,
pc_dir when from_pcdir,
pc_inc when from_pcinc,
(others=>'-') when others;
I have LPM generated 16 by 256 single port ROM for instruction memory
Code:
component mem
PORT(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
PC register port map is
Code:
pc_reg: reg Port map (clk=>clk, rst=>rst, D=>pc_din, Q=>PC, we=>ldPC);
Now the question is how can i port map the mem component because pc is 16 bit and address is 8 bit
Code:
rom: mem port map(address=>???, clock=>clk, q=>instr_din);