Port Mapping between PC and ROM as instruction memory in risc processor

[kajay]

Homework for designing risc processor. I have 16 bit PC like this

signal pc_din, PC, pc_rel, pc_dir, pc_inc : std_logic_vector(15 downto 0); -- pc datapath
pc_inc <= pc + 1;
pc_dir <= pc(15 downto 13) &  ADD;
pc_rel <=  pc_inc + ext(15 downto 0);

Mux for PC source is

with PCSrc select
pc_din <= A when from_A,
pc_rel when from_pcrel,
pc_dir when from_pcdir,
pc_inc when from_pcinc,
(others=>'-') when others;

I have LPM generated 16 by 256 single port ROM for instruction memory

component mem
PORT(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock   : IN STD_LOGIC ;
q   : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

PC register port map is

pc_reg: reg Port map (clk=>clk, rst=>rst, D=>pc_din, Q=>PC, we=>ldPC);

Now the question is how can i port map the mem component because pc is 16 bit and address is 8 bit

rom: mem port map(address=>???, clock=>clk, q=>instr_din);

 

[joelby]

Two options:

- Ignore the upper 8 bits of PC, which will make the same ROM appear at every 256 bytes.
- Decode the upper 8 bits of PC and only enable your ROM when the correct value (e.g. zero) is matched. If you have any other memories or memory mapped devices connected to the address bus, I presume you'll already have a MUX that could be used for this purpose.

Option 1 is generally fine as long as nothing else shares the address space.