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Ponder over Tech Vs Hold time Violations

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Resistance

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Hi ,

Presently its not mandatory to verify hold violations but improvement in technolgy will hold tome violations become a serious issue? with decreasing Clk to Q delay result in a hold time probs in the future..

give a thought please,
regards..
 

elecs_gene

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hi
let's discuss.first picturise the circuit of an edge triggered D flip flop.u have 4 "and" gates right..now hold is time for which the input of one "and" gate needs to be kept constant.. now,u are asking what will happen if this time is more than the propagation delay of the gates.if i am correct,the flip-flop delay includes roughly 3 gate delays.how will ever this hold time be more than propagation delay?this is again a question.. .
 

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