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POLL: Which HVL will win the race ?

Which verification language do you consider the most promising one ?

  • Verisity E (Specman)

    Votes: 0 0.0%
  • SystemC

    Votes: 0 0.0%
  • VERA

    Votes: 0 0.0%
  • SystemVerilog

    Votes: 0 0.0%
  • RAVE

    Votes: 0 0.0%
  • Sugar

    Votes: 0 0.0%
  • VHDL/Verilog (classic testbenches)

    Votes: 0 0.0%
  • SpecC

    Votes: 0 0.0%
  • A combination of two or more languages.

    Votes: 0 0.0%
  • Some other language...

    Votes: 0 0.0%

  • Total voters
    0
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tahiti

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Please state and describe your opinion...

tahiti
 

tahiti

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bah... only 4 votes

and verification is supposed to be 70% (or even more to some studies) of design effort of modern SoC systems...

well, it seems that we don't have many verification people around yet...

tahiti
 

tlihu

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I only heard of Verilog/VHDL. :cry:
 

eda_wiz

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hi,
I am sorry. But I dont know what is an HVL . can Anyone please tellme that

tnx
 

kinysh

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well, seems most of us still use verilog/vhdl to do the verification.

acutally I think the verification is limitted to the cpu speed.
so we can not verify all the corner case on verification because of speed.

to cover all the corner case, random test is really need, and long time running is also important.

so instead, I prefer to use fpga to verify the whole design for full coverage. the speed is 100:1.

bests
kinysh
 

kinysh

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ha, seems I am the first one post some opinion.
cheer!!1 :wink: :wink: :wink:
 

joe2moon

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HVL

Just like HDL stands for "Hardware Description Language", such as
Verilog and VHDL.

HVL is the abbreviation of "Hardware Verification Language", such as
OpenVera and SystemVerilog.

Maybe take a look at the following link: (0rg -> org)
h**p://www.hdlcon.0rg/index.html
 

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