In most CMOS technologies, PMOS devices are quite inferior to NMOS transistors. For example, due to the lower mobility of holes, µpCox ≈ 0,25 µnCox in modern processes, yielding low current drive and transconductance. Moreover, for given dimensions and bias currents, NMOS transistors exhibit a higher output resistance, providing moder ideal current sources and higher gain in amplifiers.
The gate-source voltage was, of course, kept constant while I was changing the source-drain voltage.Do you control / measure gate to source voltage, or do you apply source-drain voltage without paying attention of what your gate to sourec voltage is?
Well, I described how I performed the measurements as well as I could.Don't quite understand how you did your measurements.
Here are the data sheet typical values for the NMOS and PMOS devices.
The PMOS devices do have a higher conductance, but it's no more than about 40%.
Can you perform those same measurements?
View attachment 168220View attachment 168221
I'm sure it's common knowledge for a lot of people designing analog chips (which is why I asked the question on this forum). Sadly I cannot claim to have the same knowledge, hence my question.I'd consider the performance differences between NMOS and PMOS common knowledge. To quote Razavi:
In SPICE models, the lower PMOS output resistance shows specifically in channel length modulation parameter LAMBDA.
Well, according to the date I found even with these ancient devices, W = 170 um for NMOS and 360 um for PMOS, so clearly they followed that rule.It is because of mobility difference, people used to make W (gate width) larger for pMOS than for nMOS - by about 2x - 2.5x.
Then, the resistance, drive currents etc. were matched.
In latest technologies (as of 2021 - 7nm, 5nm, etc.) , this is not the case - nMOS adn pMOS have approximately same gate width (number of fins), to match their characteristics.
Hmm, OK, but even assuming that the true L is 4 to 6 um, this would still be a long channel device, I guess?10um is drawn dimension of the metal gate, the
non-self-aligned technology of the day required the
source / drain implants (or likely a wet-etched hard
masked diffusion, this was late-1970s stuff) underlap
the gate by a reliably-manufacturable extent. The
true L is probably in the 4-6um range once the S/D
diffusions are fully driven (and P outruns N, for a
shorter P channel unless the mask generation adds
some compensation - but as I said the PMOS can
be drawn shorter given its better reliability posture
and that would have been taken advantage of, by
just letting the mask extent be uncompensated.
I didn't see CD4007 models without LAMBDA parameter, e.g. this one found at LTspice@groups.io:Unfortunately the only SPICE models I was able to find for these devices were rather simplistic and show infinite output resistance...
.MODEL NMOS NMOS (
+ LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
+ RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
+ PB=.8 TOX=1200n)
.MODEL PMOS PMOS (
+ LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
+ RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
+ PB=.8 TOX=1200N)
I didn't see CD4007 models without LAMBDA parameter, e.g. this one found at LTspice@groups.io:
Code:.MODEL NMOS NMOS ( + LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m + RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p + PB=.8 TOX=1200n) .MODEL PMOS PMOS ( + LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m + RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P + PB=.8 TOX=1200N)
NMOS/PMOS Ro ratio at Id = 1 mA and Vds = Vgs is about 3.
Seemed to me he was looking for Rout
(as in gm*Rout) and not Ron (as in a
logic or switch application).
By applying 5 or 10V for Vds, you are driving the device into saturation region, not linear.
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