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PMOS / NMOS output resistance

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majormajor

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A few weeks ago I grabbed some CD4007 chips as I was curious about the characteristics of the MOSFETs contained in the chip. As it is an ancient and very simple chip, I thought I'd educate myself and see how the individual transistors would measure. Taking into account that both the NMOS and PMOS transistors are on the same piece of silicon, I was wondering how similar they were.

I measured some very basic things, such as transconductance and output resistance, with the MOSFETs biased to 1 mA drain current. I had various devices from different decades (1990's, 2000 and current).

So the NMOS and PMOS devices turned out to be fairly similar; the threshold voltages and transfer characteristics looked almost identical (for example, transconductance at Id = 1 mA: NMOS was 1.6 mA/V, PMOS 1.5 mA/V), etc. All very nice and symmetrical. However, the output resistance is very different: about 160 kOhm for the NMOS and 16 kOhm for the PMOS. I must admit I didn't expect that. That's a factor of 10 difference. All devices showed the same behaviour.

So excuse my ignorance (I don't design chips for a living) but why? I'd be interested to know. What physical property of the chip accounts for this massive difference?
 

CD4000 logic had some really long channels and
a 1-layer metallization which was also the gate.
Totally non-self-aligned. You could see a lot more
drive of the P+ boron (PMOS S/D) into the channel,
than N+ (P or As, don't know which) on the same
thermal budget. So PMOS might well be a few
microns shorter channel length when "fully baked".
PMOS being more resilient to hot carrier drift, may
have let the foundry take advantage of shorter
P processed-vs-drawn to make logic gates' area
smaller. I have seen multiple processes which
allowed drawn PMOS L < drawn NMOS L (min).

Any differences in VT would go to Ron, if FETs are
fed by the same magnitude of Vgs.
 

If I-V characteristics look alike, and threshold coltages and transconductances are close, for nMOS and pMOS transistors, their output resistances should be similar too.

How did you apply the voltages, to measure the output resistance? (Same question that Dominik asked).
 

I'd consider the performance differences between NMOS and PMOS common knowledge. To quote Razavi:
In most CMOS technologies, PMOS devices are quite inferior to NMOS transistors. For example, due to the lower mobility of holes, µpCox ≈ 0,25 µnCox in modern processes, yielding low current drive and transconductance. Moreover, for given dimensions and bias currents, NMOS transistors exhibit a higher output resistance, providing moder ideal current sources and higher gain in amplifiers.

In SPICE models, the lower PMOS output resistance shows specifically in channel length modulation parameter LAMBDA.
 

How did I measure the output resistance?

I did the most straightforward thing, measuring static DC characteristics. I disabled all CMOS pairs except one (gate to ground, source/drain open circuit). I biased VSS and VDD to about 12V so that the I/O protection diodes don't interfere with the measurements. Initially I set Vds = 5V and adjusted Vgs so that Id = 1 mA. Then I increased Vds to 6V, 7V, … 10V and monitored Id.
By the way, all measurement results look like textbook MOSFET characteristics, I'm just baffled by the factor of 10 difference in output conductance.

Numerical values:

NMOS:
Vds Id
5.0 V 999 uA
10.0 V 1030 uA
Rout = 161 kOhm

PMOS:
Vds Id
5.0V 1.0 mA
10.0 V 1.313 mA
Rout = 16 kOhm

Some data I found on 'Tinternet suggests that the geometry of these devices is PMOS L=10um, W=360um, NMOS = L=10um, W=170um, which according to my skin-deep knowledge should be way into the long channel territory, so I would have expected a higher output resistance for my PMOS friends.
 

10um is drawn dimension of the metal gate, the
non-self-aligned technology of the day required the
source / drain implants (or likely a wet-etched hard
masked diffusion, this was late-1970s stuff) underlap
the gate by a reliably-manufacturable extent. The
true L is probably in the 4-6um range once the S/D
diffusions are fully driven (and P outruns N, for a
shorter P channel unless the mask generation adds
some compensation - but as I said the PMOS can
be drawn shorter given its better reliability posture
and that would have been taken advantage of, by
just letting the mask extent be uncompensated.
 

Don't quite understand how you did your measurements.

Here are the data sheet typical values for the NMOS and PMOS devices.
The PMOS devices do have a higher conductance, but it's no more than about 40%.
Can you perform those same measurements?

1616513605105.png
1616513647716.png
 

Do you control / measure gate to source voltage, or do you apply source-drain voltage without paying attention of what your gate to sourec voltage is?
 

A thing to note is, that PMOS requires more "gate overdrive"
to reach the same drain current density (mA/um) than
NMOS owing to mobility difference, so you may be imposing
a higher (Vgs-VT) and putting the FET closer to linear region
and at a higher d(Id)/d(Vds) hence lower Rout.
 

It is because of mobility difference, people used to make W (gate width) larger for pMOS than for nMOS - by about 2x - 2.5x.
Then, the resistance, drive currents etc. were matched.

In latest technologies (as of 2021 - 7nm, 5nm, etc.) , this is not the case - nMOS adn pMOS have approximately same gate width (number of fins), to match their characteristics.
 

Do you control / measure gate to source voltage, or do you apply source-drain voltage without paying attention of what your gate to sourec voltage is?
The gate-source voltage was, of course, kept constant while I was changing the source-drain voltage.
 

Don't quite understand how you did your measurements.

Here are the data sheet typical values for the NMOS and PMOS devices.
The PMOS devices do have a higher conductance, but it's no more than about 40%.
Can you perform those same measurements?

View attachment 168220View attachment 168221
Well, I described how I performed the measurements as well as I could.
The curves you show here are not useful because they primarily show the saturated behaviour of the NMOS/PMOS devices.
I focused on something that these curves do not show:
(a) I performed the measurements at a much lower drain current(1 mA).
(b) I was interested in the linear (pentode) region of the MOSFET.
Basically, the CD4007 is primarily intended for digital use but my interest is how they behave in the linear region and as individual devices (not a pair).
 

I'd consider the performance differences between NMOS and PMOS common knowledge. To quote Razavi:


In SPICE models, the lower PMOS output resistance shows specifically in channel length modulation parameter LAMBDA.
I'm sure it's common knowledge for a lot of people designing analog chips (which is why I asked the question on this forum). Sadly I cannot claim to have the same knowledge, hence my question.
Unfortunately the only SPICE models I was able to find for these devices were rather simplistic and show infinite output resistance...
 

It is because of mobility difference, people used to make W (gate width) larger for pMOS than for nMOS - by about 2x - 2.5x.
Then, the resistance, drive currents etc. were matched.

In latest technologies (as of 2021 - 7nm, 5nm, etc.) , this is not the case - nMOS adn pMOS have approximately same gate width (number of fins), to match their characteristics.
Well, according to the date I found even with these ancient devices, W = 170 um for NMOS and 360 um for PMOS, so clearly they followed that rule.
And yes, actually the transconductance is pretty well matched (within 10%). But the output conductance is shockingly different.
These devices came out in the late 60's. The Beatles was still together!
 

10um is drawn dimension of the metal gate, the
non-self-aligned technology of the day required the
source / drain implants (or likely a wet-etched hard
masked diffusion, this was late-1970s stuff) underlap
the gate by a reliably-manufacturable extent. The
true L is probably in the 4-6um range once the S/D
diffusions are fully driven (and P outruns N, for a
shorter P channel unless the mask generation adds
some compensation - but as I said the PMOS can
be drawn shorter given its better reliability posture
and that would have been taken advantage of, by
just letting the mask extent be uncompensated.
Hmm, OK, but even assuming that the true L is 4 to 6 um, this would still be a long channel device, I guess?
 

Unfortunately the only SPICE models I was able to find for these devices were rather simplistic and show infinite output resistance...
I didn't see CD4007 models without LAMBDA parameter, e.g. this one found at LTspice@groups.io:
Code:
.MODEL NMOS NMOS (
+ LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
+ RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
+ PB=.8 TOX=1200n)

.MODEL PMOS PMOS (
+ LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
+ RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
+ PB=.8 TOX=1200N)

NMOS/PMOS Ro ratio at Id = 1 mA and Vds = Vgs is about 3.
 
"I was interested in the linear (pentode) region of the MOSFET"

By applying 5 or 10V for Vds, you are driving the device into saturation region, not linear.

You should apply high (nominal) Vgs, and small Vds (50 mV or 0.1 V), to measure Rdson - the ON resistance in the linear region of operation.
 

Seemed to me he was looking for Rout
(as in gm*Rout) and not Ron (as in a
logic or switch application).
 

I didn't see CD4007 models without LAMBDA parameter, e.g. this one found at LTspice@groups.io:
Code:
.MODEL NMOS NMOS (
+ LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
+ RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
+ PB=.8 TOX=1200n)

.MODEL PMOS PMOS (
+ LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
+ RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
+ PB=.8 TOX=1200N)

NMOS/PMOS Ro ratio at Id = 1 mA and Vds = Vgs is about 3.

Thanks for the models, they are certainly better than what I had.
Funnily enough, if I had seen a factor of 3 difference in Ro, I would have probably accepted it without thinking too much about it. But a factor of 10? So I'm still a bit baffled.
--- Updated ---

Seemed to me he was looking for Rout
(as in gm*Rout) and not Ron (as in a
logic or switch application).

Yes, exactly. (Actually the whole query was prompted by a circuit that uses the MOSFETs in the CD4007 in a small-signal linear application. I saw some unexpected imbalance between currents that were supposed to be roughly the same and eventually I traced it to the Rout difference between the PMOS and NMOS devices.)
--- Updated ---

By applying 5 or 10V for Vds, you are driving the device into saturation region, not linear.

Surely you mean "at 5 or 10V for Vgs", not "Vds".
 
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