Thank you for your reply. Sorry for late response from my side because I need to take care other subjects.
I have recalculated the size of the transistors. I attached in this post.
I updated the schematic drawing with some node names for clarity.
with this sizing, all transistors are in saturation except for M6-M7 in cutoff, M8-M9 in triode, M10-M11 in triode.
All transistor which are in saturation take 70uA as expected from calculation, except the long tail transistor which takes double of that, 140uA.
For general analog design, the L used is typically 2-3 times the minimum length. This choice is a good trade-off between speed and gain.
What do you mean when you say Vbias? are they the input common mode? you have a current reference already, use it as basis and mirror those currents at each branch for the desired bias current. Normally in today's circuits, power budget is the primary concern so once you've determined how much the circuit should disippate then you can determine the bias currents at each branch (Itotal=P/V). From this you can determine which topology to use (i.e. I need high gain, high slew rate, then I'd like to try a coscoded amplifier with push-pull output to see if I reach my specs).
As a starting guide, In allen's book "CMOS Analog Circuit Design, 3rd ed." shows a popular design procedure for a 2 stage op-amp. (chapter 6).
I meant by Vbias-es are all those 4 Vbias in the schematic to bias the long tail transistor M5, M3-M4, M11-M10, and low voltage cascode current source M6-M9.
In order to make all transistor in saturation, should I change the biasing transistor size or the size of the transistor which are not in saturation?
from derivation of low voltage cascode current source, I got this: VSG7 - Vt9 <= Vbias2 <= VSG7 + Vt9 - VSG9. This formula is the guidance to chose Vbias2 so VDS9 not more than Vt1.
I looked at your schematic. The bias reference caught my attention. Are you sure it works?
I recalculated the size and yes, it works. see the picture in this post.
The BJT PNP2 Emitter area is 8x larger than that of PNP1.
both branch, left and right, have 70uA right now and all MOSFET are in saturation.
You don't use tables from books to design. You have your own technology, so you should use that technology's parameters.
I am not sure whether what I am doing is correct or not. But what I did was I simulated single MOSFET, both PMOS and NMOS, and see the uoCox from simulation result.
it helps me to predict the current and during sizing.
Biases are consequence of the other parameters of the design.
I am totally beginner in this so I would like to ask.
is it a misleading way of thinking if I consider all biasing transistors (the ones in the green box) as a merely voltage supply for other transistor which have more important function with regards to the spec?
if no, I think I can adjust the size to get the proper bias voltages for Vbias2,3, and 4. is that the correct way in designing this analog ic?
II am thinking that way because the MOSFET in the folded cascode part are not in saturation. I guess it is because incorrect biasing voltages.
I really appreciate any suggestion.