Nov 7, 2014 #1 S seamoss Junior Member level 3 Joined Jun 14, 2012 Messages 26 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,453 I am seeing an condition in my simulation where the PMOS gate is higher than n-well. Can this cause a potential problem ? S/D are however lower than n-well.
I am seeing an condition in my simulation where the PMOS gate is higher than n-well. Can this cause a potential problem ? S/D are however lower than n-well.
Nov 7, 2014 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 Should be ok, as long as the max. permitted G-B, G-S & G-D voltages aren't exceeded.
Nov 8, 2014 #3 D dick_freebird Advanced Member level 7 Joined Mar 4, 2008 Messages 9,006 Helped 2,333 Reputation 4,685 Reaction score 2,526 Trophy points 1,393 Location USA Activity points 71,711 An unexpected D-S leakage (GIDL) could be seen in reality, but neglected in modeling.