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PMOS gate higher than substrate

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seamoss

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I am seeing an condition in my simulation where the PMOS gate is higher than n-well. Can this cause a potential problem ? S/D are however lower than n-well.
 

Should be ok, as long as the max. permitted G-B, G-S & G-D voltages aren't exceeded.
 

An unexpected D-S leakage (GIDL) could be seen in
reality, but neglected in modeling.
 
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