PMOS gate higher than substrate

[seamoss]

I am seeing an condition in my simulation where the PMOS gate is higher than n-well. Can this cause a potential problem ? S/D are however lower than n-well.

 

[erikl]

Should be ok, as long as the max. permitted G-B, G-S & G-D voltages aren't exceeded.

 

[dick_freebird]

An unexpected D-S leakage (GIDL) could be seen in
reality, but neglected in modeling.