[SOLVED] Plz review my simple code of 10 lines related to D Flip Flop

[moonnightingale]

Hi
I have written a code.
Can some body just see the code and confirm me that it is ok
The Circuit diagram is also attached for which code is written.

module logiccircuit(A,B,Y,YY,X,XX,clock);
output reg A,B,Y,YY;
input X,XX,clock;
reg E,F;
always@(posedge clock)
begin
E=((A&~X)|(A&~B)|(~A&B&X));
F=(B^X);
A<=E;
B<=F;
Y<=A;
YY<=B;
end
endmodule

 

[FvM]

For clarity, I would prefer logical instead of bitwise operators although the difference doesn't matter here.

The code differs from the schematic by adding registers for Y and YY, delaying the output for one clock cycle. Place the assignments outside the clock synchronous always block to comply with the schematic.

There's no actual purpose of regs E and F in your code.

 

[moonnightingale]

For clarity, I would prefer logical instead of bitwise operators although the difference doesn't matter here.

The code differs from the schematic by adding registers for Y and YY, delaying the output for one clock cycle. Place the assignments outside the clock synchronous always block to comply with the schematic.

There's no actual purpose of regs E and F in your code.

Thanks a lot FVM
I have made correction of Bitwise

module logiccircuit(A,B,Y,YY,X,XX,clock);
output reg A,B,Y,YY;
input X,XX,clock;
reg E,F;
always@(posedge clock)
begin
E=((A&&!X)|(A&&!B)|(!A&&B&&X));
F=(B^X);
A<=E;
B<=F;
Y<=A;
YY<=B;
end
endmodule

Can u kindly explain me the other thing by making change in code
If i will place assignments outside always block,how D Flip Flop will work?
Thanks a lot for guiding me

 

[moonnightingale]

Ok this is final code but still getting error

Thanks a lot.I have understood ur point and have removed extra nodes
and taken Y and YY out
but i am getting error now. Plz help me

module logiccircuit(A,B,Y,YY,X,XX,clock);
output reg A,B,Y,YY;
input X,XX,clock;
assign Y=A;
assign YY=B;
always@(posedge clock)
begin
A<=((A&&!X)|(A&&!B)|(!A&&B&&X));
B<=(B^X);
end
endmodule
Error
ERROR:HDLCompilers:246 - "logiccircuit.v" line 24 Reference to scalar reg 'Y' is not a legal net lvalue
ERROR:HDLCompilers:53 - "logiccircuit.v" line 24 Illegal left hand side of continuous assign
ERROR:HDLCompilers:246 - "logiccircuit.v" line 25 Reference to scalar reg 'YY' is not a legal net lvalue
ERROR:HDLCompilers:53 - "logiccircuit.v" line 25 Illegal left hand side of continuous assign

 

[FvM]

You either need to remove the reg attribute from the outputs Y and YY. Or place it in a "combinational" always @(*) block. Or omit Y and YY that aren't but simple copies of A and B.