Honestly I'm not sure what you are trying to accomplish here, but using verilog as a parser for vcd is not what you want to do. Here is a site with some PLI routines and one of them happens to be a VCD reader.
I have no clue what the contents of a .vec file are so I can't even fathom if you could read it into Verilog, but like I said already, Verilog makes a really poor parser. Use C or some scripting language like Python/Perl to change the .vec file into something you can read from Verilog, or start searching for a .vec PLI reader (nothing comes up when I searched for that).