tetooo
Newbie level 3
Plz help. Vhdl code
I want a structural VHDL code of 1 to 16 Demultiplexers. with an active low Enable signal using 1 to 2 Demultiplexer. [ use Generate statement]
______________________________________________________________
Also I need a structure and behavior VHDL code of 5-bits binary counter with a synchronous load signal to preset the counter to a specific initial state. the output of the counter ( Q0 to Q4) are connected to a binary decoder that shows the state of the counter.
I want a structural VHDL code of 1 to 16 Demultiplexers. with an active low Enable signal using 1 to 2 Demultiplexer. [ use Generate statement]
______________________________________________________________
Also I need a structure and behavior VHDL code of 5-bits binary counter with a synchronous load signal to preset the counter to a specific initial state. the output of the counter ( Q0 to Q4) are connected to a binary decoder that shows the state of the counter.
Last edited: