pls help check my verilog code for fractional-n pll with sdm

[jasonxilion]

i am new to design fn pll.and i wrote some verilog coeds of the segma-delta modulation.
but the result is wrong,i guess,but not sure
how to know the result right or wrong?

i post my code here,pls heip point out the mistakes if there are.



//define constant
`define add1 10
`define add2 10
`define add3 11
`define add4 13
`define add5 12
`define add6 12
`define gain_pos 11'b00001100100
`define gain_neg 11'b11110011100
//module start
module sdm_CRFF3(clk,data_out,reset,data_in,add1_out,add2_out,
add3_out,add4_out,add5_out,add6_out,);
//define input pin
input clk;
input reset;
input [`add1:0] data_in;
//define output bit stream
output [`add6:0] data_out;
output [`add1:0] add1_out;
output [`add2:0] add2_out;
output [`add3:0] add3_out;
output [`add4:0] add4_out;
output [`add5:0] add5_out;
output [`add6:0] add6_out;
//define register
reg [`add1:0] in_reg;
reg [`add1:0] fb_reg;
reg [`add2:0] add2_reg;
reg [`add3:0] add3_reg;
reg [`add4:0] add4_reg;
reg [`add5:0] add5_reg;
reg [`add6:0] add6_reg;
//define wire
wire [`add1:0] add1_wire;
wire [`add2:0] add2_wire;
wire [`add3:0] add3_wire;
wire [`add4:0] add4_wire;
wire [`add5:0] add5_wire;
wire [`add6:0] add6_wire;
wire [`add1:0] add1_in;
wire [`add2:0] add2_in;
wire [`add3:0] add3_in;
wire [`add4:0] add4_in;
wire [`add5:0] add5_in1;
wire [`add5:0] add5_in2;
wire [`add6:0] add6_in;
wire bit_ctl;
//input register
always @(negedge reset or posedge clk)
begin
if (!reset) in_reg=0;
else
in_reg=data_in;
end
//feedback bit control
always @(posedge clk)
begin
if (bit_ctl) fb_reg<=gain_neg;
else
fb_reg<=gain_pos;
end
assign add2_in=fb_reg+in_reg;
//first stage adder
assign add2_wire=add2_in+add2_reg;
always @(negedge reset or posedge clk)
begin
if (!reset) add2_reg<=0;
else
add2_reg<=add2_wire;
end
assign add3_in={{2{add2_wire[10]}},add2_wire[9:0]};
//second stage adder
assign add3_wire=add3_in+add3_reg;
always @(negedge reset or posedge clk)
begin
if (!reset) add3_reg<=0;
else
add3_reg<=add3_wire;
end
assign add4_in={{3{add3_wire[11]}},add3_wire[10:0]};
//third stage adder
assign add4_wire=add4_in+add4_reg;
always @(negedge reset or posedge clk)
begin
if (!reset) add4_reg<=0;
else
add4_reg<=add4_wire;
end
assign add5_in1={{2{add2_wire[10]}},add2_wire[9:0],1'b0};
//output stage
assign add5_in2={{2{add3_wire[11]}},add3_wire[10:0]};
assign add5_wire=add5_in2+add5_in1;
assign add6_in={{2{add4_wire[13]}},add4_wire[12:2]};
assign add6_wire=add6_in+add5_wire;
assign data_out=add6_wire;
assign bit_ctl=~{add6_wire[11]&reset};
assign add1_out=in_reg;
assign add2_out=add2_wire;
assign add3_out=add3_wire;
assign add4_out=add4_wire;
assign add5_out=add5_wire;
assign add6_out=add6_wire;
endmodule