PLL power v.s. frequency

[u931803]

Hello guys,

I have nearly no knowledge in the design of PLL, so the following question came across when I tried to decide how to design the clock of my project

Suppose two clocks are mandatory: clk and clk_2x where the frequency of clk_2x is two times that of clk
Now for some reason I need either (1) a single clock clk_4x or (2) three clocks clk_p45, clk_p90 and clk_p135, in which pXX means phase shift

Considering the difficulty to design such PLL, the power consumption, and the potential routing problem, can anyone tell me if which option is better?
If clk_4x can be as high as 1.6GHz, will the answer be the same?

Thanks a lot

 

[D.A.(Tony)Stewart]

PLL generates new clock by multiplying reference xN by an Integer counter / N in the feedback loop to the mixer.

Thus clk_4x is the VCO output which drives /4 counter to mix at 1x phase detector and vco/2 counter out to get clk_2x

However to get a 3 phase output requires a divide by 3 counter with 3 gate combinations to generate each phase at 120deg with 50%, or as required.

The PLL could generate a clock using N= 3 or 6, if I understand your question but has additional 3 phase logic for 3 phase clocks.