PLL Charge pump static offset

[kakbydima]

Hello there,

Have charge pump PLL. Usually from books the static offset is defined by current mismatch and PFD reset time (i.e., dT = dI/Ip*Treset, where Ip is the mean charge pump current). Basically, if the net current injected into the loop filter is zero, then we have zero static offset. What I found out on practice is that the clock feedthrough, specifically current induced by it to the output is not equal between rise and fall of a control signal (either up or down). And clock feedthrough contribution to the overall offset is drastic compared to charge pump DC mismatch. Any idea how this could be mitigated? (I minimized the switch sizes as much as it is allowed by voltage drop, placed them on the source side of the current source)

 

[dick_freebird]

I'd start with whether you care about static
offset when the phase is controlled by a
feedback loop. What if any consequence
from that error term (divided by loop gain)?

There are things you can spend a lot of time
"fixing" that don't deliver any benefit. Is this
one of them?

 

[ahsrabrifat]

I think you can use a fully differential charge pump. https://ieeexplore.ieee.org/document/4541451

 

[kakbydima]

Hi dick_freebird,

Thanks for the response.
First of all, I apologize, by static offset I implied static phase offset/error that is induced by non-idealities of PFD+charge pump. As far as I understand, loop gain does not affect the static phase error.
Regarding the need to fullfil it: it is required by application to have certain static phase error.
While the current mirror random mismatch and channel length modulation induced mismatch is described to be the main contributors to static phase error, the clock feedthrough is x10 larger

I'd start with whether you care about static
offset when the phase is controlled by a
feedback loop. What if any consequence
from that error term (divided by loop gain)?

There are things you can spend a lot of time
"fixing" that don't deliver any benefit. Is this
one of them?

 

[kakbydima]

I think you can use a fully differential charge pump. https://ieeexplore.ieee.org/document/4541451

Hi ahsrabrifat,

Thanks for the reply. I will take a look at the paper.

 

[dick_freebird]

For charge pump clock feedthrough, look into
"source steering" the "pump" (time-gated current
is not really that; no "pumping", just "allowing").

Applying full-rail gate drive to control current
has the drawback of blowing the edges through
to the next stage (and it's a fussy one).

Make your "switch" a diff pair and drive it with
as low a swing as necessary, take your current
off the other side and only see the source-step
(hundred mV instead of >1V). You may also
benefit from edge softening there, to keep
dV/dt coupling down. Especially if fRef is low,
there's a lot of "gap" between what's needed
and what's done in a simpleminded bang-bang
switch.