pll phase-noise/ rms phase error

In a Phase-modulation scheme,rms phase error is very critical,it should be less than 2deg in most cases.

This rms phase error directly relates to in-loop phase noise of pll output.

while working with PLL frequency synthesizer, we come across two formulae to calculate phase noise:


1) in-loop PLL_PhaseNoise[dBc/Hz] = Noise floor[dBc/Hz]+ 10*LOG(Comparison Frequency[Hz]) + 20*LOG(N)

noise floor in this formula is synthesizer

2) phase-noise= reference phase noise + 20*log(N)

Now, the question is which formula to consider for comparing a measured phase-noise at PLL output,secondly the VCO
phase-noise is not accounted in above formulae, does that mean that reference phase noise or synthesizer noise floor control
the final phase noise? What if I use a VCO with better close-in phase noise,will I get any improvement in final phase noise,how do
I consider vco phase-noise this in above formulae?

eg. reference phase noise =-135dBc/Hz
Noise floor =-210 dBc/Hz
Fc= 10MHz
N=44
then from 1) PN=107 dBc/Hz
2) PN=102 dBc/Hz

Where as measured phase noise is about -90 dBc/Hz at 10 KHz offset for a carrier of 4GHz.
Why the measured phase-noise is off by 12 dB ? where to look for improvement?