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PLL design in 30khz~50khz

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louiee

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Hi everyone,
I would like to ask, is it possible to design PLL which the carrier frequency is around 30khz to 50khz (input.Freq. for PFD)? what are the issues for PLL if designed in such frequency? bcoz normally PLL is used in frequency of Mhz range.

thanks in advance,


louiee
 

kak111

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CMOS RF SYNTHESIZER PLL

The synthesizer will generate a 3:1 frequency range anywhere from 300Hz to 4,000,000Hz (4MHz)

CMOS RF SYNTHESIZER

Regards KAK
 

louiee

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thanks for your help,
i am sorry if it is not clear, now i try to design PLL which designed using CMOS 0.18um technology (ic design not a system design) for the application of ranging from 30khz to 50khz. my concern is, normally PLL which I found designed on chip is applied on the Mhz range (high frequency) of application such as fiber optic receiver. so, is it possible to design this PLL in low frequency? what are the issues?

thanks
louiee
 

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