please send me asic design flow and fpga design flow

adilkhan123 · Oct 25, 2008

asic design flow

please send me asic design flow and fpga design flow

pmat · Oct 26, 2008

Hi,
ASIC Flow:
**broken link removed**
FPGA Flow:
**broken link removed**

Pavlos

ljxpjpjljx · Oct 27, 2008

asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow

amitk3553 · Jun 7, 2013

ljxpjpjljx said:
asic flow: RTL coding-> RTL simulation-> synthesis->dft insert->formal->STA->gate simulation->backend flow

It means DFT is before LEC(formal verification)????

What is the meaning of gate simulation???

onion2014 · Jun 8, 2013

is ASIC design from quartet is the same with that from synopsis

pmat said:
Hi,
ASIC Flow:
**broken link removed**
FPGA Flow:
**broken link removed**

Pavlos

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