Please help me with my clock driver design

[chemaphy]

Hello all,

I am now designing a clock driver for a folding interpolation ADC. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver??

Thanks for your help,
chemaphy

 

[satyasiva]

I think u should not connect clock driver output directly to i/p of 32 compatrators. B'cos the clock driver o/p cap. will increases. so use buffers between them.

 

[Meridian]

I think u should not connect clock driver output directly to i/p of 32 compatrators. B'cos the clock driver o/p cap. will increases. so use buffers between them.

Buffers are absolutely a must. Use cmos types.

 

[yibinhsieh]

You can use the clock tree format to drive the comparators.

But you need to carefully take care the layout matching issue.

It will affect your dynamic performance in such high frequency.

Usually, the inverter size is like 1-->3-->9.

Yiibn.