bus bridge in CPLD
I have a ADSP-BF533 processor, with internal SDRAM controller. The proc has one single bus inerface, for all the external peripherals, and mem. It has all the signals for everything.
As I see now in the UG, the ext bus has select signals, for SDRAM, and other 4 for peripherals. it is fine!
In this case, could I use a CPLD? With a fast separated 3state buffer? as an asinchronous memory-like device, with ready signal.
So, the CPLD (or whatever else) has to do the bus bridging only. In the proc side, there is the proc, and mem, and in the other side, there are the slow peripherals, in a slow 10-15MHz bus.
Do I need a bus bridge? Or, can I connect them directly? In many DSP boards, there is a CPLD, with some bus-function. What should they do in the buses?
What If I will have to design (in the far future, not now) a system without a this-like good ext-bu-IF? Will I have to produce these select signals? with what? Is it possible in this speed?