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Please help me with designing a bus bridge in CPLD

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buenos

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bus bridge in CPLD

Hi!

I have to design a system bus interface and an address decoder, for the ADI's Blackfin processor in a CPLD. it has a 133MHz system bus. I have to connect a 133MHz SDRAM, and some low speed peripherals (USB/ethernet controllers, max 12/50MHz). The DSP will be the bus master. The USB-IF can be temporally a bus master, but it is not necessary. I would like to use a xilinx Coolrunner CPLD.

--Is it possible to make a 133MHz bus interface logic in a cpld? Is a Coolrunner fast enough for this? (the datasheet said: 5.7 ns pin-to-pin delays, and max 250MHz)

As I know, the 250MHz test system consists of one gate, and nothing else. But my IF will be more difficoult. So I think it will work slower. I do not wait an exact speed, only an estimated.

--What should do the bus-IF logic?

I can think it very simply (a clock prescaler, and some gates for the READY signal), but there are very difficoult bus-IF implementations, with dual port memories, and other... Like the OPB/PLB bridge for the Microblaze processor. Why need they that level of difficulity?

--Can I connect the SDRAM directly to the system-bus? (with address decoded-CS-signal from the CPLD) The processor ha a universal interface for DRAM, SRAM and other, and it has an integrated SDRAM controller.

--How can I know the required size of the CPLD?


--Will the CPLD address decoder decrease the system performance, and SDRAM access speed? Through an increased clk to CS (clk to address) SKEW. What should I do?
 

mc&fpga

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Re: bus bridge in CPLD

as isee ,you want to communicate sdram and other bus like usb,...
as you know you need a sequncer for controlling the refresh timiing of sdram and the another sequncer for controlling the bus timming like usb or ethernet,
you will have problem to use coolrunner and other cpld for thier low macrocell,
and you need memory to control asynchrounce interface,so cpld and coolrunner aren't good device.
 

buenos

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bus bridge in CPLD

I have a ADSP-BF533 processor, with internal SDRAM controller. The proc has one single bus inerface, for all the external peripherals, and mem. It has all the signals for everything.

As I see now in the UG, the ext bus has select signals, for SDRAM, and other 4 for peripherals. it is fine!

In this case, could I use a CPLD? With a fast separated 3state buffer? as an asinchronous memory-like device, with ready signal.

So, the CPLD (or whatever else) has to do the bus bridging only. In the proc side, there is the proc, and mem, and in the other side, there are the slow peripherals, in a slow 10-15MHz bus.

Do I need a bus bridge? Or, can I connect them directly? In many DSP boards, there is a CPLD, with some bus-function. What should they do in the buses?

What If I will have to design (in the far future, not now) a system without a this-like good ext-bu-IF? Will I have to produce these select signals? with what? Is it possible in this speed?
 

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Re: bus bridge in CPLD

ya,the dsp processor like ti c6000 and youranalog device processor like adsp have some peripheral to control the sdram or ddr bus,and they are cheap way to connect the memory and other bus(like ethernet), ya in some boards only for i/o buffering and implement other bus controlling like usb they use cpld (and for low power system they use collrunner),and cpld permit us in designingt to control the i/o port.as you said you don't need them for contrlloing sdram (cause adsp do that).so you don't need them in fast speed.
 

buenos

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Re: bus bridge in CPLD

thanx again.

and what about the bridging between the 133MHz and the 15MHz bus? Is enough a fast bus-switch (select) and a clock prescaler? ready-signal logic? or do I need some temporal memory-buffering? or not?

If I would use without bus-sw, when the dsp takes back the select from the low-sp.per., it may go out from the bus slowly. (bus crash) And they need slower clk.

What do you think in that:



select signal
----------------------------
I I
I system bus V (en) slow bus
[DSP]---------------------[bus-sw]----------------------
I I I I
[sdram] [other hs] [lowsp.per.1] [lowsp2]



I hope it looks visible.

Added after 1 minutes:

as I see it don't look like, how I draw.
:(

Added after 11 minutes:

I can not draw it, because the forum-system does not allow multiple spaces in the text.

another trying:


Code:
       select signal 
   ------------------------------------
   I                                  I 
   I       system bus                 V (en)         slow bus 
[DSP]-----------------------------[bus-sw]---------------------------------------
             I            I                       I                      I 
        [sdram]        [other hs]           [lowsp.per.1]              [lowsp2]
 

mc&fpga

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Re: bus bridge in CPLD

as i see from your note,
you want and you can control sdram in speed of 133 mhz,and interface the data to
another bus,so you need an asynchrounse memory in your dsp processor or dma protochol in your dsp processor to control the speed of i/o bus in low speed,
 

buenos

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bus bridge in CPLD

is it possible that the processor can access to the sdram at high speed, and on the same bus, it can access to the perif at low speed?
It has async memory control signals, like the ready signal. I saw that. only by waiting some cycles, as it do an access to the perif?
do not needed any external logic? buffers, switches?
 

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