Please help me on this guyz (STA !!!)

[mohdfayez]

Hi guyz, the STA tool reports WNS and No. of violating paths. I'd like to know what are the other ways to correct the violating paths even if timing optimization fails in removing that path.

Q2: How can we calculate the delay of such violating path. If the delay consists of the gate delay and net delay then is it possible that we can manually remove the gates that have maximum delay?

Is the gate delay of each cell given in standard LEF?


help appreciated guys.

 

[avimit]

There exists a number of ways to correct a timing failure
1). placing the critical path cells closer in layout
2). introducing pipline registers
3). write parallel RTL
4). register re-timing
5). state machine encoding
6). cell resizing
7). redundant resigters to imporve driving current. etc etc...
8). Aviod unwanted priority encoding: vey common in RTL while writing -if-else-if statments, and while writing loops.
9). use fast arithmatic circuits, if the critical path does include arithmatic.

If you manually remove the cells with or without max delay, you wont have same functionality? would you?

LEF does not have timing info.
Kr
Avi
http://www.vlsiip.com

 

[energeticdin]

Hope
www.vlsiip.com will be helpfull

 

[mohdfayez]

Hi thanks for the reply.. can u explain me more on register re-timing (how is it practically achieved)? and by cell resizing do u mean changing the TU percentage of the cell?

Agree LEF does not contain the timing info, what I wanna if required to find the delay through any path how can we go about finding that?

Thanks, Fayez.

Added after 8 minutes:

sorry need to reframe my question.

I hope timing library contains all the gate delays and net delays in your layout. Please correct me on this?

Now in case we are not meeting timing even after time opt, can we play with these delays to meet timing?

What i meant by deleting cells with max delay was removing the footprint cells which should not effect the functionality.

I am very confused on this concept actually please do help

 

[mohdfayez]

@ Avimit

Hi can you please clear me on these concepts? I'd really appreciate.. thanks

 

[cafukarfoo]

Hello mohdfayez,

Normally, we will try to solve the STA violation in backend design first. Then if physical design changes cannot help the STA violation, then engineer will force to go back to fix the RTL coding( this is not recommended cause once RTL change, you need to do your backend design again ).

Delete the cell and change the cell with the same footprint won't help you here. If the tool can swap it for you to fix this violation, then it will swap it. It remain there for a reason.

So few thing you can try in backend design.
1. Identiy the worst negative slack path.
2. Check the physical placement and routing of the cell. Check whether it is due to the bad placement or bad routing. If yes, fix this, extract spef and rerun STA again.
3. Cause during synthesis, this path should pass before the synthesis engineer pass the gate level netlist to the backend.
4. If there is still violation, then you can consider skew to improve your STA violation.
5. You can also check with the synthesis guy on the slack for this path during synthesis.

Hope this give you some idea.