Please check if the following code is correct

[JacquesKleynhans]

The following code is an IO data flow controller for to and from sram and FPGA.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dataflow_control is
port
(
	state_enable		: in    std_logic;
	output_enable	: in    std_logic;
	camera_clk	: in    std_logic;
	readclk		: in    std_logic;
	data_in		: in    std_logic_vector(7 downto 0);
	data_inout	: inout std_logic_vector(7 downto 0);
	data_out	: out   std_logic_vector(7 downto 0)
);
end dataflow_control;

architecture behavior of dataflow_control is

signal data_in_reg	:std_logic_vector(7 downto 0);
signal data_out_reg	:std_logic_vector(7 downto 0);

begin


	process(camera_clk,state_enable,data_in)
		begin
		if (state_enable = '1' and rising_edge(camera_clk)) then
				data_in_reg <= data_in;
		end if;
	end process;

	process(readclk,state_enable,data_out_reg)
		begin
		if (state_enable = '1' and rising_edge(readclk)) then
				data_out <= data_out_reg;
		end if;
	end process;

	process(output_enable,data_inout,data_in_reg)
		begin
			if output_enable = '1' then
				data_inout <= "ZZZZZZZZ";
				data_out_reg <= data_inout;
			else
				data_inout <= data_in_reg;
				data_out_reg <= data_inout;
			end if;	
	end process;			
			
end behavior;

Kind Regards

Added after 4 hours 49 minutes:

Please Anyone,

I get these erros

W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W MO111 tristate driver data_inout_3[7] on net data_inout[7] has its enable tied to GND (module dataflow_control) dataflow_control.vhd (34) camera_payload_1.srr (59) 19:44:00 Mon Jun 14 ProASIC3E Mapper
W CL159 Input data_in is unused dataflow_control.vhd camera_payload_1.srr 19:43:57 Mon Jun 14 compilerReport
W CL169 Pruning Register data_in_reg(7 downto 0) dataflow_control.vhd (27) camera_payload_1.srr (41) 19:43:57 Mon Jun 14 compilerReport
W CD434 Signal data_in_reg in the sensitivity list is not used in the process dataflow_control.vhd (39) camera_payload_1.srr (39) 19:43:57 Mon Jun 14 compilerReport

[/quote]

 

[manojkartik]

hi

which xilinx version are you using? Mine is xilinx webpack 11.1, your code synthesized properly without any errors or warnings on mine

regards

 

[JacquesKleynhans]

I am actually using an actel device...

Hmmm thats strange that it worked fine on yours

Ill try again to simulate.

Thx for the reply

 

[elec4fun]

I don't see any problem.

This is what Quartus synthesized :
**broken link removed**

 

[JacquesKleynhans]

Thx for checking guys, I think the problem is when I simulate the code inside my top it clashes with the inout and the output signal. Check the pics

 

[JacquesKleynhans]

Otherwise you can check my other post CONNECTING SRAM , CAMERA MODULE , PIC AND FPGA

Added after 4 hours 20 minutes:

well i think its working, changed my sram things are looking up, touch wood.....

 

[zula]

your code didnt create the tri-state buffer. if wanna use the bidirectional signal you should the create tri-state.
i suggest you to design the bidir signal like that;

tri <= datainreg when outputenable = '1' else
"ZZZZZZZ";

 

[ayuanshop]

It's successful with 4 warnings in my PC

Added after 4 seconds:

It's successful in my PC