PLB Master module is not operating correctly (250 points!)

[BlackOps]

plb master

Hello,

I am using EDK 9.1 and ISE 9.1, my hardware is XUPV2P board

I have generated the PLB Master module peripheral, with the peripheral wizard. Now i want the master module to transfer data from the DDR memory connected to the system to the slave register of the Master module.

attached picture is the snapshot of the address space range of my EDK system.

Here is how the VHDL code generated by peripheral wizard says to do it:

===================
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the source data address (local) to the ip2ip register
-- 3. write the destination address (remote) to the ip2bus register
-- - note: this address will be put on the target bus address line
-- 4. write 0x0004 to the length register
-- 5. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 6. write 0x0a to the go register, this will start the write operation
=====================

here is a piece of my code:

=====================================================================================
Xuint32 data; // variable for test

// PREPARATION!
// Set the base address of the DDR to a visible value. We will manipulate it later.
XIo_Out32(0xd0000000, 0xABCD1234);

// Write another distinctive value into the first reg (slv_reg0) of the peripheral.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + 0x00, 0xAABBCCDD);

data = XIo_In32(0xd0000000);
xil_printf("Value of the DDR (before master transfer) = : %x\r\n", data);

data = XIo_In32(XPAR_VIDEO_CTRL_0_BASEADDR + 0x00);
xil_printf("Value of the slv_reg0 (before master transfer) = : %x\r\n", data); 

// COMMANDING THE MASTER!
// Write 0x40 to the control register on the master peripheral
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x00, 0x40);

// Write the source address for the write to the IP2IP register on the master peripheral
// In our example, we'll use slv_reg0 in the peripheral.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x04, XPAR_VIDEO_CTRL_0_BASEADDR + 0x00);

// Write the destination address for the write to the IP2BUS register on the master peripheral
// In our example, we'll overwite the same BRAM location that we set earlier.
XIo_Out32(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x08, 0xd0000000);

// Write the length of the transfer (in bytes) to the LENGTH register on the master peripheral
// In our example, we only want to send one word (4 bytes).
XIo_Out16(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0C, 0x04);

// Write a value for the byte enables to the BE register on the master peripheral
// In our example, we are writing to a 0x???????0 address, so we'll use half of the 64 bit PLB
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0E, 0xf0);

// Write the special "GO" command into the GO Register on the master peripheral
// The GO command is always 0x0A
XIo_Out8(XPAR_VIDEO_CTRL_0_BASEADDR + master_reg_offset + 0x0F, 0x0A);

// Wait to see what happens! The DDR address containing 0xABCD1234 should be overwritten with 0xAABBCCDD

data = XIo_In32(0xd0000000);
xil_printf("Value of the DDR (AFTER master transfer) = : %x\r\n", data);
===================================================================================

i used the UART port to print the values, here is what i get when the above code is executed:

===============
Value of the DDR (before master transfer) = : ABCD1234
Value of the slv_reg0 (before master transfer) = : AABBCCDD
Value of the DDR (AFTER master transfer) = : 0
===============


As you see from the code, i am writing the value of 0xABCD1234 to the DDR memory with address - 0xd0000000 (take a look at the address space range picture snapshot attached to this webcase) and this value is successfully written and later being read from the DDR memory before the master operation.

I also write the value of 0xAABBCCDD to the slv_reg0 register. And see that slv_reg0 really contains this value.

Next, i am commanding the master to start the master operation! I am reading 4 bytes from slv_reg0, and sending them to DDR with the address 0xd0000000!

Now! i am trying to read the DDR address 0xd0000000, and i see that it contains the value of 0 (ZERO)!

i dont understand why does the master write value of 0 to the DDR?? maybe the problem is very trivial? where could be my mistake? or the master module doesnt work good with DDR memory? (but it should..)

p.s. same happens when i try to read the DDR memory and write its contents to the slv_reg0 register... slv_reg0 register has the value of 0 (zero) after the master operation...

any ideas? anyone have done it successfully?

Everything looks correct...though...maybe problem is very trivial? maybe there is some small mistake which i dont see, but it looks correct!

this problem really annoys! I hope you have understood my problem, and my purpose of this project. if anyone helps me to perform this operation successfully i donate 250 points to him.

Same thing happens when i want to write values to BRAM instead of the DDR.. BRAM is being written with zeroes by the master module!! :|

 

[BlackOps]

xilinx plb master uart

well... no at least any replies for such a big time. engineers from xilinx say that it should work...and just send me projects of same functionality, which actually dont work in my case, even though i run them "as is" ... alternative solution, is to use another custom IPIF interface. By the way, Xilinx IPIF interface is also too slow... thanx anyway.

 

[atena]

xio_in32 bram

Can you upload your whole design so that i can have a proper check.... Thanks

 

[BlackOps]

xilinx plb master slow

Oh, thanks alot for your effort to help , but i have refused to use this interface long time ago. it is not effective and fast. i prefer custom IPIF interface.